M1 Pro MacBook Power-On Sequence | A2442 820-02098

What this A2442 power-on reference covers

The A2442 is a 14-inch MacBook Pro using the M1 Pro platform. This reference was captured on a working 820-02098 logic board. It begins at the USB-C port with no battery connected and follows the board through CD3217 startup, charger operation, MPMU/SPMU sequencing, SoC awake rails, embedded SMC activity, NAND power, USB-C 20V negotiation and the late display and wireless enables.

The sequence is divided into six practical diagnostic stages. The full overview below shows the relationship between all 60 checkpoints; the six larger diagrams provide readable voltage, timing, test-point and function details.

How to use the master schematic and stage diagrams

• Numbered circles: show the measured operating order; they are not schematic net numbers. Compound labels such as 20-1 or 29-4 identify substeps within a larger stage.
• Arrows and connecting lines: show how an input, enable, clock, reset or data bus affects the next circuit block.
• Master schematic: use it to trace dependencies between CD3217, ISL9240, MPMU/SPMU, Viper/MONACO, NAND and the M1 Pro SoC.
• Six stage diagrams: use them for the measured time, expected voltage or waveform, test point and practical meaning of each checkpoint.
• Last confirmed checkpoint: begin diagnosis immediately after the last condition that is known to be correct.

A multimeter is suitable for stable rails and enables. SPI, I2C, SPMI, clock activity and short-lived pulses require an oscilloscope or logic analyser. A normal DC average does not prove that a digital waveform is valid, and a brief output pulse does not by itself prove that the regulator producing it is faulty.

A2442 820-02098 master power-on diagnostic schematic

This is the working circuit map used by IT-Tech Online during difficult A2442 repairs, particularly when a fault crosses more than one power-on stage. It links the initial USB-C path to CD3217 ROM activity, PPDCIN_AON, ISL9240 boost and buck operation, PPBUS_AON, MPMU/SPMU startup, SoC awake rails, embedded SMC communication, NAND power and SoC ROM access.

Use this master schematic first to identify which circuit should create the missing condition and what must arrive before it. Then open the corresponding stage diagram below for the measured voltage, waveform, timing and test point. This prevents a late missing rail from being mistaken for a failed SoC when the actual cause is an earlier enable, input supply, reset, clock or communication bus.

The schematic is an independent measured repair reference, not an Apple service document. Exact timing can vary, but the dependency chain makes it especially valuable for boards that partially start, pulse and shut down, negotiate 20V without booting, or reach some SoC rails while later outputs remain absent.

Stage 1 — USB-C input and PPBUS_AON boost

The sequence starts with PPVBUS_USBC0 at 5V. The CD3217 port controller creates PP3V3_UPC0_LDO and reads its external UF260 ROM through SPI. Valid ROM activity allows power to pass into PPDCIN_AON, which supplies the U5200 ISL9240 charger stage.

CD3217 and ACE-ROM startup

The first USB-C power stage involves more than simply receiving charger voltage. Hardware-level dead-battery Rd on CC1 or CC2 allows the charger to detect the MacBook and supply the default 5V VBUS. CD3217 then generates PP3V3_UPC0_LDO, starts from its internal boot ROM and reads the external ACE-ROM patch and configuration through SPI.

For the complete sequence—including ACE-ROM loading, SPI measurements, CC1/CC2 behaviour, 5V power-path control, 20V negotiation and common no-PPDCIN_AON fault patterns—read our detailed CD3217 and ACE-ROM power-on sequence guide.

Stage 1: USB-C input, CD3217 initialization and PPBUS_AON generation on a working A2442 board 820-02098.

After CHGR_AUX_DET and CHGR_VDDP satisfy the charger prerequisites, U5200 operates in boost mode and creates approximately 12.3V PPBUS_AON. P3V8AON_PWR_EN then enables U5700 to create PP3V8_AON, the supply required for the following PMU stage. See the complete ISL9240 power-on sequence for current sensing, measured voltages, test points and fault-isolation steps.

Where to look when Stage 1 stops

• No PPVBUS_USBC0: check the charger, cable, connector and input path.
• 5V is present but PP3V3_UPC0_LDO is missing: inspect the selected CD3217 controller and its local power path.
• The LDO is present but SPI clock and chip-select activity are absent: inspect the CD3217 ROM circuit and the controller startup conditions.
• PPDCIN_AON reaches U5200 but PPBUS_AON does not rise: verify CHGR_AUX_DET, CHGR_VDDP, the ISL9240 circuit and PPBUS loading.
• PPBUS_AON is correct but PP3V8_AON is missing: check P3V8AON_PWR_EN, U5700 and its output rail.

Stage 2 — MPMU, SPMU, always-on and S2 rails

With PP3V8_AON stable, the U8100 master PMU must have adequate PMU_VDDHI. It then builds PP1V8_AON, receives the 32 kHz MPMU clock, and creates PP1V2_AON and PP3V3_AON. PMU_CRASH_L should remain high during a normal startup.

The sequence then advances into the S2 state with PP1V2_S2, PP5V_S2_MAIN and PP0V72_S2_VDDLOW. PMU_CLK32K_SOC supplies the low-frequency clock used by the SoC/SMC domain. A missing clock can produce an abnormal fixed-current pattern even when several DC rails appear normal.

Stage 2 diagnostic approach

Start with PMU_VDDHI and the first AON output rather than checking every S2 rail at once. If PP1V8_AON is missing, later PMU outputs cannot be judged. If the AON group is present but all S2 rails are absent, check PMU state control and the MPMU/SPMU prerequisites. If one S2 rail alone is absent, inspect that regulator’s input, enable, output resistance and load.

Stage 2 begins when U5700 converts PPBUS_AON into PP3V8_AON. See the complete MPMU, SPMU, always-on and S2 power sequence for measured timings, voltages, test points and fault-isolation steps in details.

Stage 3 — Viper, MONACO and SoC awake rails

U8100 wakes and enables the U9300 Viper controller with P1V8VDDH_SLP_L and P1V8VDDH_PWR_EN. CLVR_RESET_L releases the MONACO regulators from reset. U9300 then drives the DRMOS stages to produce PP1V8_S1_CLVR_VDDH.

That 1.8V rail powers the MONACO regulators responsible for CPU, CPU SRAM, GPU, GPU SRAM and ANE awake-switch rails. PPVDD_FABRIC_S1 and PPVDD_AFR_CS_S1 complete the related SoC S1 group. Because several outputs appear within a very small time window, an oscilloscope is much more useful than a multimeter when rails pulse and collapse.

See the complete Stage 3: Viper, MONACO and SoC awake power sequence

When the awake rails pulse and disappear

A short-lived output does not automatically prove that U9300, a DRMOS stage or the SoC is shorted. Confirm whether the enable and reset signals remain asserted, whether PP1V8_S1_CLVR_VDDH is stable, and whether the next PMU status checkpoint appears. A later fault can command the PMU to shut the group down, making a healthy regulator look defective.

Stage 4 — Embedded SMC and SoC ROM startup

At approximately 3.2 seconds in this capture, U8100 asserts PMU_RESET_L, PMU_SYS_ALIVE and PMU_ACTIVE_READY. These signals do not have identical roles. PMU_RESET_L and PMU_ACTIVE_READY are important for embedded SMC and SoC ROM activity, while PMU_SYS_ALIVE also feeds SSD and other downstream power logic.

After the SoC clock is available, SPI_SOCROM_1V8_CS_L confirms that the SoC ROM is being selected. The board then develops IPD_PWR_EN_PMU, SPMI communication and the I2C buses used for charger control, USB-C negotiation and NAND PMIC configuration.

Stage 4 begins when U8100 releases the M1 Pro from reset and confirms that the PMU is ready. The SoC receives its 24MHz reference clock, reads the external U2010 SoC ROM and starts embedded-SMC communication with the charger, CD3217 controllers and NAND PMIC. See the detailed Stage 4 embedded SMC and SoC ROM startup guide.

Useful separation between ROM and NAND faults

A board may show SoC ROM chip-select activity yet still fail to produce NAND rails. In that case, do not restart the diagnosis at USB-C input. Check PMU_SYS_ALIVE, I2C_NAND_PMIC_SDA_1V8, the NAND PMIC supplies and the NAND regulator outputs. Conversely, missing SoC ROM activity with correct early rails directs attention to PMU_RESET_L, PMU_ACTIVE_READY, the SoC clock and ROM circuit.

Stage 5 — NAND power and USB-C 20V negotiation

After NAND PMIC communication, UN400 creates PP1V2_NAND0 and PP0V9_NAND0. P2V5_NAND0_EN allows UN480 to create PP2V5_NAND0. NAND0_RESET_L and NAND0_CLK24M_R then confirm reset release and clock delivery to the storage devices.

At about 4.4 seconds in this capture, I2C communication with the port controller leads to PPDCIN_AON rising from 5V to 20V. PPVDD_AVEMSR_AWAKESW follows, and U5200 later changes PPBUS_AON from its initial boost condition to approximately 12.0V buck-mode operation.

Stage 5 creates the NAND power rails and prepares the internal storage for operation. In parallel, CD3217 negotiates 20V with the USB-C charger and U5200 changes PPBUS_AON from boost to buck regulation. See the detailed Stage 5 NAND power and USB-C 20V negotiation guide.

Why 20V does not prove a complete boot

Successful USB-C 20V negotiation confirms important SMC-to-CD3217 communication, but it does not prove that NAND, display or operating-system startup is healthy. The capture also shows that missing SSD rails do not necessarily prevent the adapter from negotiating 20V. Use 20V as a checkpoint, not as a final diagnosis.

Stage 6 — Display, backlight and wireless enables

LCD_PWR_EN, BL_PMIC_PWR_EN and PP1V2_AWAKESW_BLC appear around 5.8 seconds, followed by BL_PWR_EN. These checkpoints separate a board that has reached the display stage from one that stopped earlier during PMU, SoC ROM or NAND startup.

I2C_SEEPROM_SDA appears later as part of display identification. The reference also records a late change in PPVDD_AVEMSR_AWAKESW and, finally, WLBT_PWR_EN for Wi-Fi and Bluetooth. BL_PMIC_PWR_EN may drop when no display assembly is connected, so interpret that signal together with the test configuration.

Quick diagnostic table: use the last confirmed checkpoint

Measurement and safety notes

• Confirm the exact board number before using a test point; component designators can change between board revisions.
• Record the charger, battery and display connection state because they affect late-stage behaviour.
• Use a high-impedance probe and a stable ground point. Poor probing can distort clocks and communication buses.
• Do not inject voltage into a rail until its normal voltage, power source and connected loads are understood.
• When an enable pulses, capture the input, enable and output together. The order often distinguishes a regulator fault from a commanded shutdown.

Frequently asked questions

Does this sequence apply to every M1 or M1 Pro MacBook?

No. The diagnostic method is reusable, but this timing and these test points are specifically measured from an A2442 board 820-02098. Other Apple-silicon boards can use different PMUs, port-controller arrangements, signal names and timing.

Why does PPDCIN_AON begin at 5V and later rise to 20V?

The board first starts from the charger’s default USB-C voltage. After the embedded controller and communication path are operating, the CD3217 port controller negotiates the higher adapter voltage.

Why does PPBUS_AON measure about 12.3V first and about 12.0V later?

With only 5V input available, the ISL9240 initially operates in boost mode. After 20V negotiation, it changes to buck-mode operation, producing a slightly different PPBUS_AON level.

Are the millisecond values pass-or-fail specifications?

No. They are reference timings from one known-good capture. The order and dependencies are more useful diagnostically than expecting every healthy board to match each timestamp exactly.

Continue with the related repair guides

Compare this Apple-silicon sequence with the earlier Intel Mac charger and PPBUS_G3H startup sequence, the Intel MacBook SMC circuit, and the MacBook logic-board power-rail guide. To see how power-sequence diagnosis is applied to real faults, visit our Apple-silicon MacBook logic-board repair case studies.

Need professional diagnosis? IT-Tech Online provides component-level MacBook logic-board repair in Melbourne, including mail-in service for customers outside Melbourne.