M1 Pro Viper & MONACO Power Sequence | A2442 820-02098
Last updated: 16 August 2026
Stage 3 of the A2442 M1 Pro power-on sequence begins after the MPMU and SPMU have created the required always-on and S2 rails. MPMU U8100 then releases U9300 Viper and the three MONACO regulator blocks. U9300 drives three DrMOS phases to create PP1V8_S1_CLVR_VDDH, and this 1.8V high-current supply allows UA100, UA200 and UA500 to produce the CPU, GPU, ANE, SRAM and SoC fabric awake rails.
This guide follows a measured working 14-inch MacBook Pro A2442 logic board 820-02098. It explains the control-signal order, Viper three-phase power stage, MONACO rail ownership, practical test points and the current-reading patterns that help separate an MPMU control fault from a Viper, DrMOS, MONACO or downstream-load fault.
Read the preceding MPMU, SPMU, always-on and S2 power sequence, or return to the complete A2442 M1 Pro power-on sequence.
Measured times and current values are working-board references, not universal pass-or-fail specifications. Charger, battery, board temperature, software state and capture trigger can change the observed values.
Table of Contents
Where Stage 3 begins and ends
Stage 3 begins after PP0V72_S2_VDDLOW is present. At this point the Stage 2 prerequisites include stable PP3V8_AON, PP1V8_AON, PP1V2_AON, PP3V3_AON, PP1V2_S2 and PP5V_S2_MAIN.
The Stage 3 sequence then performs three jobs:
- MPMU U8100 releases and enables U9300 Viper and releases the MONACO regulators from reset.
- U9300 and the three DrMOS power stages create PP1V8_S1_CLVR_VDDH.
- MONACO UA100, UA200 and UA500 create the first CPU, GPU, ANE, SRAM and SoC-fabric awake rails.
Stage 3 ends before PMU_RESET_L, PMU_SYS_ALIVE and PMU_ACTIVE_READY appear. Those signals, together with the SoC-ROM access sequence, belong to Stage 4.
Stage 3 sequence overview
Stage 3 prerequisites
Do not start by replacing U9300 or a MONACO IC merely because a CPU or GPU awake rail is missing. First confirm the rails that supply and control this stage.
| Prerequisite | Expected condition | Why it matters |
|---|---|---|
| PPBUS_AON | Stable system bus | Supplies the high-current conversion path |
| PP3V8_AON | Approximately 3.8V | Required for PMU operation and control sequencing |
| PP1V2_S2 | Approximately 1.2V | Supplies digital and CLVR support domains |
| PP5V_S2_MAIN | Approximately 5.1V | Supplies U9300 and the DrMOS gate-driver domains |
| PP0V72_S2_VDDLOW | Approximately 0.72V | Last measured Stage 2 checkpoint before Stage 3 begins |
| Stage 3 output resistance | No short on PP1V8_S1_CLVR_VDDH or the awake rails | Prevents immediate protection and rail collapse |
MPMU control signals that release Stage 3
U8100 controls the transition into the Viper and MONACO stage. Three signals appear almost together, but they perform different functions.
P1V8VDDH_SLP_L
P1V8VDDH_SLP_L rises to approximately 1.2V at about 3168ms. The _L suffix means active low. Therefore, a high level deasserts the sleep condition and allows U9300 to wake.
If P1V8VDDH_SLP_L remains low, U9300 is intentionally held in sleep even if its supply rails are present. The measured sequence may stop with PMU rails jumping or disappearing, and PMU_RESET_L will not follow.
P1V8VDDH_PWR_EN
P1V8VDDH_PWR_EN rises to approximately 1.2V at about 3168.001ms. This is the direct power-enable request for the U9300 conversion stage.
On the reference capture, failure at this boundary can cause the initial 5V input current to fall from roughly 0.35A to about 0.12A. These numbers are diagnostic examples, not fixed specifications; the important pattern is that the board attempts Stage 3 and then drops back to a lower current state.
CLVR_RESET_L
CLVR_RESET_L also rises to approximately 1.2V at about 3168.001ms. It releases MONACO UA100, UA200 and UA500 from reset. CLVR_RESET_L is controlled by the MPMU; it is not generated by U9300.
This distinction matters:
- PP1V8_S1_CLVR_VDDH missing: diagnose the Viper and DrMOS power path.
- PP1V8_S1_CLVR_VDDH present but CLVR_RESET_L low: diagnose MPMU state, reset control and Stage 2 stability.
- 1.8V and reset both present but awake rails missing: move to MONACO support supplies, rail loads and controller communication.
U9300 Viper controller
U9300 is identified by the schematic as an RAA225502A Viper controller. The board populates three PWM channels. PWM4 through PWM8 are not used in this implementation, even though related BOM variants can support different phase counts.
Viper is an Apple functional codename and is not expanded as an acronym in the schematic. Its job in this stage is to regulate the 1.8V high-current supply used by the local SoC regulator blocks.
U9300 supplies and monitoring
U9300 receives the main switching input through PPVIN_P1V8VDDH_ISNS, uses PP5V_S2_MAIN for its controller and driver-related supply, and uses the lower-voltage support domains for logic and signalling. Its schematic also exposes:
- P1V8VDDH_IMON for current monitoring
- P1V8VDDH_ISENSE1, ISENSE2 and ISENSE3 for phase-current feedback
- P1V8VDDH_DRMOS_TSENSE for power-stage temperature information
- P1V8VDDH_DRMOS_FAULT_L for aggregated DrMOS fault status
- P1V8VDDH_FAULT_L for controller/output fault status
- P1V8VDDH_ILIMIT_THROTTLE_L and P1V8VDDH_TLIMIT_THROTTLE_L for current- and temperature-limit signalling
These feedback paths explain why U9300 may receive an enable but still refuse to create the output: a short, missing current-sense path, power-stage fault or thermal indication can stop the conversion sequence.
P1V8VDDH_DRMOS_EN and PWM outputs
At approximately 3174ms, U9300 asserts P1V8VDDH_DRMOS_EN to approximately 5.1V. U9300 then drives P1V8VDDH_DRMOS_PWM1, PWM2 and PWM3.
A multimeter can confirm that DRMOS_EN is present, but it cannot prove PWM timing or phase activity. Use an oscilloscope to inspect PWM1–PWM3 and the corresponding switch nodes.
How the three DrMOS phases work
U9400, U9420 and U9500 are integrated DrMOS power stages from the RAA225701B family. DrMOS combines a gate driver, high-side MOSFET and low-side MOSFET in one package. Each stage receives:
- PP5V_S2_MAIN for its driver supply
- A shared P1V8VDDH_DRMOS_EN signal
- One PWM input from U9300
- Bootstrap and switch-node components
- Current-sense and temperature-sense connections back to U9300
Phase ownership
| Phase | DrMos | Inductor path | Control | Feedback |
|---|---|---|---|---|
| Phase 1 | U9400 | L9400 | PWM1 | ISENSE1 / RISNS1 |
| Phase 2 | U9420 | L9420 | PWM2 | ISENSE2 / RISNS2 |
| Phase 3 | U9500 | L9500 | PWM3 | ISENSE3 / RISNS3 |
The three phase outputs combine into PP1V8_S1_CLVR_VDDH. Low-value 0.005Ω shunts and the DrMOS sense outputs allow current monitoring and phase balancing. A fault in one phase can prevent startup, create an unstable 1.8V rail or force the controller to shut down all phases.
PP1V8_S1_CLVR_VDDH
At approximately 3180ms the combined output reaches about 1.8V. This is not a CPU core voltage. It is the high-current 1.8V supply used by the MONACO regulator blocks, which then create lower and dynamically controlled SoC rails.
If DRMOS_EN and PWM are present but PP1V8_S1_CLVR_VDDH remains at 0V, check:
- Resistance from PP1V8_S1_CLVR_VDDH to ground with all power removed.
- PP5V_S2_MAIN at U9400, U9420 and U9500.
- The three PWM inputs and switch nodes.
- P1V8VDDH_DRMOS_FAULT_L and individual phase-fault paths.
- The three inductors, sense shunts and output capacitors.
- The VDDH inputs and bypass capacitors of UA100, UA200 and UA500.
What MONACO does
MONACO is Apple’s schematic codename for the local multi-output regulator ICs that sit close to the M1 Pro SoC power domains. It is not documented as an acronym. The three populated MONACO instances share PP1V8_S1_CLVR_VDDH but own different downstream rail groups.
Each MONACO also requires its local digital, I/O, clock, reset and control conditions. A correct 1.8V VDDH rail therefore does not prove that its awake outputs must appear.
UA100 MONACO 0: CPU rails
UA100 supplies the performance-CPU regulator domains. The measured timeline records:
- PPVDD_PCPU0_AWAKESW: CPU awake power, practical measurement near CA141.
- PPVDD_PCPU_SRAM0_AWAKESW: CPU SRAM awake power; this node can be difficult to access directly.
The schematic also shows additional configured CPU and CPU-SRAM outputs. When all UA100 outputs are missing, inspect UA100 VDDH, local support rails, CLVR_RESET_L and the controller interface. When only one output is missing, check the resistance and capacitors on that specific rail before replacing UA100.
UA200 MONACO 1: GPU rails
UA200 owns the GPU regulator domains. The measured checkpoints are:
- PPVDD_GPU0_AWAKESW: GPU awake power, accessible near CA242.
- PPVDD_GPU_SRAM0_AWAKESW: GPU SRAM awake power.
The schematic includes configured GPU0/GPU1 and corresponding SRAM outputs. Their operating voltage can change with SoC state, so confirm that the rail appears and remains stable rather than relying on one universal DC value.
UA500 MONACO 4: ANE, fabric and AFR rails
UA500 supplies several SoC internal domains, including:
- PPVDD_ANE0_AWAKESW: Apple Neural Engine awake power, accessible near CA540.
- PPVDD_ANE0_SRAM_AWAKESW: ANE SRAM awake power.
- PPVDD_FABRIC_S1: SoC interconnect-fabric S1 rail.
- PPVDD_AFR_AWAKESW: Apple-defined AFR awake domain.
The measured reference table also groups a later AFR/CS S1 checkpoint. Apple does not provide a public expansion for every internal domain name, so retain the schematic net name rather than inventing an acronym.
Why the MONACO awake voltages are not listed as one fixed value
The original capture confirms that the CPU, GPU and ANE awake outputs appear around 3180ms, but it does not provide a single fixed voltage for each rail. These are local SoC power domains and can change with power state, workload, silicon configuration and regulator programming.
For board diagnosis, use four observations:
- Does the rail appear in the correct sequence?
- Does it remain stable long enough for Stage 4 to begin?
- Is its resistance-to-ground comparable with a known-good board?
- Does the rail collapse together with its input supply, or independently?
A low resistance on a modern SoC core rail is not automatically a short. Compare like-for-like measurements and do not inject an assumed voltage into an unknown SoC rail.
Complete measured Stage 3 order
| Step | Time | Signal or rail | Expected | Test point | Meaning | If missing |
|---|---|---|---|---|---|---|
| 21 | 3168ms | P1V8VDDH_SLP_L | ≈1.2V high | R9331 | MPMU releases U9300 from sleep | Viper remains asleep; sequence stops |
| 22 | 3168.001ms | P1V8VDDH_PWR_EN | ≈1.2V | R9330 | MPMU enables U9300 | No Viper power stage; current may fall back |
| 23 | 3168.001ms | CLVR_RESET_L | ≈1.2V high | PPU8B2 | Releases UA100, UA200 and UA500 | MONACO stays in reset |
| 24 | 3174ms | P1V8VDDH_DRMOS_EN | ≈5.1V | PP9262 | U9300 enables all three DrMOS stages | No DrMOS switching |
| 25 | After enable | P1V8VDDH_DRMOS_PWM1/2/3 | PWM waveforms | Controller-to-DrMOS paths | Three phase-drive signals are active | Owning phase cannot switch |
| 26 | 3180ms | PP1V8_S1_CLVR_VDDH | ≈1.8V | Output inductors / rail capacitors | Three-phase Viper output is established | MONACO cannot create awake rails |
| 27 | ≈3180ms | PPVDD_PCPU0_AWAKESW | Dynamic awake rail | CA141 | UA100 CPU output | CPU awake power missing |
| 28 | ≈3180ms | PPVDD_PCPU_SRAM0_AWAKESW | Dynamic awake rail | Difficult to access | UA100 CPU-SRAM output | CPU SRAM power missing |
| 29 | ≈3180ms | PPVDD_GPU0_AWAKESW | Dynamic awake rail | CA242 | UA200 GPU output | GPU awake power missing |
| 30 | ≈3180ms | PPVDD_GPU_SRAM0_AWAKESW | Dynamic awake rail | Rail capacitor | UA200 GPU-SRAM output | GPU SRAM power missing |
| 31 | ≈3180ms | PPVDD_ANE0_AWAKESW | Dynamic awake rail | CA540 | UA500 ANE output | ANE awake power missing |
| 32 | ≈3180ms | PPVDD_ANE0_SRAM_AWAKESW | Dynamic awake rail | Rail capacitor | UA500 ANE-SRAM output | ANE SRAM power missing |
| 33 | After MONACO start | PPVDD_FABRIC_S1 | Dynamic S1 rail | Rail capacitor | SoC fabric power | SoC fabric rail missing |
| 34 | After MONACO start | PPVDD_AFR / AFR_CS_S1 domain | Dynamic S1 rail | Rail capacitor | AFR/CS power domain | Associated SoC rail missing |
Rail ownership and fault isolation
| Missing signal or rail | Primary owner | First checks |
|---|---|---|
| P1V8VDDH_SLP_L / PWR_EN | MPMU U8100 | Stage 2 rails, PMU state and control path |
| CLVR_RESET_L | MPMU U8100 | PMU state, reset path and rail stability |
| P1V8VDDH_DRMOS_EN / PWM1–3 | U9300 Viper | U9300 supplies, input enable, fault and sense paths |
| PP1V8_S1_CLVR_VDDH | U9300 plus U9400/U9420/U9500 | Output resistance, three phases, driver supply and DrMOS faults |
| CPU/CPU-SRAM awake rails | UA100 MONACO 0 | VDDH, reset, local support rails and CPU-rail load |
| GPU/GPU-SRAM awake rails | UA200 MONACO 1 | VDDH, reset, local support rails and GPU-rail load |
| ANE/ANE-SRAM/FABRIC/AFR rails | UA500 MONACO 4 | VDDH, reset, local support rails and individual output loads |
Recommended diagnostic order
- Confirm the complete Stage 2 rail set is stable.
- With power removed, check PP1V8_S1_CLVR_VDDH and each accessible awake rail for an abnormal short.
- Power the board and measure P1V8VDDH_SLP_L at R9331.
- Measure P1V8VDDH_PWR_EN at R9330 and CLVR_RESET_L at PPU8B2.
- Confirm U9300 input and support supplies.
- Measure P1V8VDDH_DRMOS_EN.
- Use an oscilloscope to compare PWM1, PWM2 and PWM3.
- Inspect the three switch nodes and confirm all populated phases participate.
- Confirm PP1V8_S1_CLVR_VDDH reaches approximately 1.8V.
- Check the VDDH input at UA100, UA200 and UA500.
- Measure the accessible CPU, GPU and ANE awake rails.
- Stop at the last confirmed checkpoint and diagnose the immediate owner before moving to Stage 4.
Common Stage 3 fault patterns
| What you observe | Most useful interpretation |
|---|---|
| Stage 2 rails correct but SLP_L remains low | MPMU has not released Viper or is responding to an earlier fault |
| SLP_L high but PWR_EN missing | MPMU state/control issue; U9300 has not received the conversion request |
| PWR_EN present but DRMOS_EN missing | U9300 supply, internal startup, current/temperature feedback or output-load fault |
| DRMOS_EN present but PWM1–3 absent | U9300 fault state or missing controller prerequisite |
| One PWM or switch node missing | Individual U9300 output, DrMOS, bootstrap, phase inductor or sense-path fault |
| All phases pulse and stop | PP1V8_S1_CLVR_VDDH short, MONACO VDDH short, phase fault or over-current protection |
| PP1V8_S1_CLVR_VDDH correct but every awake rail missing | CLVR_RESET_L, MONACO support supply, shared control/clock or simultaneous local fault |
| Only CPU rails missing | UA100 or the CPU/CPU-SRAM output loads |
| Only GPU rails missing | UA200 or the GPU/GPU-SRAM output loads |
| Only ANE/fabric/AFR rails missing | UA500 or the corresponding output loads |
| Input current rises near 0.35A then falls near 0.12A at 5V | Reference failure pattern around Viper enable; verify the exact last signal rather than replacing parts from current alone |
Terminology used in this guide
| Term | Full name or meaning | Function in Stage 3 |
|---|---|---|
| Viper | Apple functional codename | U9300 three-phase controller for PP1V8_S1_CLVR_VDDH |
| MONACO | Apple functional codename | UA100, UA200 and UA500 local SoC regulator blocks |
| DrMOS | Driver MOSFET integrated power stage | Combines the gate driver, high-side MOSFET and low-side MOSFET |
| PWM | Pulse-Width Modulation | U9300 phase-control waveform sent to each DrMOS |
| CLVR | Apple regulator-domain net prefix; commonly interpreted as closed-loop voltage regulation | Names the local regulator supply, reset and support domains |
| VDDH | High supply-voltage domain | 1.8V high-current input used by MONACO |
| S1 | Board power-state S1 domain | Power state assigned to the VDDH and SoC-fabric rails |
| AWAKESW | Awake-state switched rail | Rail enabled when the associated SoC block enters the awake state |
| PCPU | Performance CPU cluster | Performance-core CPU power domain |
| GPU | Graphics Processing Unit | Graphics power domain |
| SRAM | Static Random-Access Memory | Local memory power domain associated with CPU, GPU or ANE |
| ANE | Apple Neural Engine | Neural-processing power domain |
| FABRIC | SoC interconnect fabric | Internal data interconnect power domain |
| AFR | Apple-defined SoC domain; expansion not published in this schematic | Local awake/S1 output group supplied by UA500 |
| ISENSE | Current Sense | Phase-current feedback used for balance and protection |
| TSENSE | Temperature Sense | Power-stage temperature feedback |
| IMON | Current Monitor | Analogue indication of regulator current |
| OTP | One-Time Programmable configuration | Defines device-specific phase and output behaviour |
| _L suffix | Active-low signal | The named function is asserted when the signal is low |
Frequently asked questions
Is PP1V8_S1_CLVR_VDDH a CPU core rail?
No. It is the 1.8V high-current feed for the MONACO local regulators. MONACO then creates the CPU, GPU, ANE, SRAM and fabric rails.
Does U9300 directly create the CPU and GPU voltages?
No. U9300 and its three DrMOS phases create PP1V8_S1_CLVR_VDDH. UA100, UA200 and UA500 create the downstream awake rails.
Are the three Viper phases always equally active?
The hardware has three populated phases, but exact phase participation is controller- and load-dependent. Compare PWM1–3 and the three switch nodes with an oscilloscope rather than assuming identical activity at every moment.
Can a missing MONACO rail cause the complete 1.8V VDDH rail to collapse?
Yes. A shorted MONACO output, damaged MONACO input or excessive downstream load can cause U9300 to enter over-current protection and shut down the shared VDDH supply.
Why is CLVR_RESET_L high before the 1.8V VDDH rail is fully established?
The MPMU controls reset and Viper enable as part of one programmed transition. The measured timing difference is only a few milliseconds. The MONACO blocks still require their supply conditions before their outputs can operate.
Can current draw alone identify the failed component?
No. Current draw can identify the approximate failure boundary, but the same current pattern can be caused by a missing enable, regulator fault, output short or controller protection. Confirm the last signal and rail in sequence.
Measurement and safety notes
Use DC voltage measurements for the MPMU control signals, DRMOS_EN, PP1V8_S1_CLVR_VDDH and static support rails. Use an oscilloscope for PWM1–3, switch nodes, clocks and short-lived rail activity.
Disconnect all power before resistance or diode-mode testing. Modern SoC rails can have naturally low resistance; compare with a known-good board of the same configuration.
Do not inject 1.8V into a downstream CPU, GPU or ANE rail merely because the shared VDDH input is 1.8V. The MONACO outputs may be substantially lower and dynamically controlled. Do not attach a grounded oscilloscope reference to a floating switch node.
Continue to Stage 4
After the Viper output and MONACO awake rails are stable, MPMU U8100 asserts PMU_RESET_L, PMU_SYS_ALIVE and PMU_ACTIVE_READY, allowing the embedded SMC and SoC-ROM startup sequence to begin. Return to the complete A2442 820-02098 M1 Pro power-on sequence and continue from the last confirmed checkpoint.
