Intel Mac SMC Circuit: Startup and PPBUS_G3H Adjustment
This component-level guide explains how the discrete System Management Controller starts on an older MagSafe Intel Mac and how it participates in PPBUS_G3H regulation. It begins with the SMC power, clock and reset prerequisites and ends when SMC_PM_G2_EN enables the next standby-power stage.
Quick answer
On the 820-00165 reference board, confirm PP3V42_G3H, PP3V3_S5_SMC_VDDA, PP1V2_S5_SMC_VDDC, the 12 MHz SMC crystal, the separate 32 kHz clock, SMC_RESET_L and PP3V3_S5_AVREF_SMC. After U7100 asserts SMC_BC_ACOK, the SMC communicates with U7100 over the charger SMBus and raises PPBUS_G3H from its approximately 8.1 V base level to the board’s 8.6 V target. A running SMC then asserts SMC_PM_G2_EN at approximately 3.3 V.
The principal example is the 2015–2017 13-inch MacBook Air A1466 logic board 820-00165. The diagnostic method applies to many earlier Intel Macs with a discrete SMC, but signal names, component designators and PPBUS targets vary by model.
Scope limit: this is not the startup architecture used by T2 or Apple silicon Macs. Start with the preceding ISL6259 charger-to-PPBUS_G3H guide, then continue to the PM_SLP_S4_L timing guide.
Apple silicon Macs use a substantially different PMU, embedded-SMC and SoC power architecture. See the complete M1 Pro A2442 820-02098 power-on sequence and Apple silicon logic-board repair case studies.
Table of Contents
What the SMC controls during early startup
The SMC is a board-specific microcontroller that supervises power states, charging, batteries, temperatures, fans, sensors, keyboard and lid events. During early startup it must first receive valid supply rails and clocks, leave reset, recognise a valid adapter, communicate with the charger controller and then enable the next standby-power stage.
The important diagnostic rule is to locate the first missing prerequisite. A missing SMC_PM_G2_EN signal is the final symptom of several earlier conditions and does not, by itself, prove that U5000 is defective.
SMC startup sequence at a glance
| Stage | Signal or rail | 820-00165 reference | What it proves |
|---|---|---|---|
| 1. Main G3Hot supply | PP3V42_G3H | Approximately 3.42 V | The always-on source is available at the SMC supply domain. |
| 2. SMC power domains | PP3V3_S5_SMC_VDDA and PP1V2_S5_SMC_VDDC | Approximately 3.3 V and 1.2 V | The SMC analog and core supply pins are powered. |
| 3. Clock sources | SMC_EXTAL/SMC_XTAL and SMC_CLK32K | 12 MHz oscillation and a separate 32 kHz clock | The SMC has its main oscillator and G3Hot timing clock. |
| 4. Reset released | SMC_RESET_L and PP3V3_S5_AVREF_SMC | Both approximately 3.3 V | U5110 accepts the supply and is no longer holding U5000 in reset. |
| 5. Adapter valid | SMC_BC_ACOK | High, approximately 3.3 V | U7100 has accepted the charger input. |
| 6. Charger regulation | SMC_BC_SCL/SDA and PPBUS_G3H | Communication activity; PPBUS rises from about 8.1 V to about 8.6 V | The SMC and U7100 are communicating and the charger accepts the programmed target. |
| 7. Next power stage | SMC_PM_G2_EN | Approximately 3.3 V at R8140 | The SMC permits U7501 to create the following standby rails. |
1. SMC power rails on U5000
PP3V42_G3H reaches the U5000 VBAT and always-on supply domain. The same source passes through L5001 to the rail named PP3V3_S5_SMC_VDDA, which supplies the SMC analog domain. The U5000 VDDC pins also require PP1V2_S5_SMC_VDDC at 1.2 V.
U5000 SMC supply and clock section on 820-00165. The controller requires its G3Hot power domains, clock inputs and released reset before it can manage the next power state.
Checkpoint: measure all three supply domains at their local decoupling components or inductors, not only at a distant rail. If one rail is low, disconnect power and determine whether its source is missing or its load has low resistance to ground before selecting the SMC as a suspect.
2. The 12 MHz crystal and 32 kHz clock are different
Y5110, R5110, C5110 and C5111 form the SMC’s 12 MHz oscillator between SMC_EXTAL and SMC_XTAL. This is the main crystal circuit. The schematic also shows SMC_CLK32K as a separate 32 kHz input used for G3Hot timing and wake functions.
Use an oscilloscope with a low-capacitance probe and a short ground connection. Probing a crystal node with excessive capacitance can stop or distort the oscillator, so compare both sides and confirm the probe itself is not creating the fault.
3. U5110 releases SMC_RESET_L and creates AVREF
U5110 is the SMC reset supervisor. PP3V42_G3H reaches its V+ input and its VIN monitor path through R5127. The schematic specifies an approximately 3.0 V detection threshold. When the monitored rail is valid and the manual-reset inputs are inactive, U5110 releases pin 5 and SMC_RESET_L rises through the R5100 pull-up.
C5101 is connected to the DELAY pin and controls the reset timing on this reference circuit; R5101 is marked OMIT. The MR1 and MR2 inputs must both be low to force a manual reset. U5110 REFOUT also creates PP3V3_S5_AVREF_SMC, the 3.3 V reference used by the SMC analog measurement circuits.
Checkpoint: expect SMC_RESET_L and PP3V3_S5_AVREF_SMC to be approximately 3.3 V. If AVREF is present but reset remains low, inspect U5110’s VIN, V+, reset inputs, R5100 pull-up, C5101 and any loading on SMC_RESET_L.
4. Power, clock and reset do not prove the SMC firmware is running
Valid supply rails, clocks and a high SMC_RESET_L prove that the external startup conditions are present. They do not prove that U5000 has executed its firmware, initialised its buses or accepted every monitored condition. Confirm operation by checking meaningful SMC inputs, communications and outputs rather than treating one static voltage as a complete test.
5. SMC_BC_ACOK and MagSafe one-wire are separate paths
U7100 asserts SMC_BC_ACOK after it accepts the charger input. The SMC uses this as an adapter-valid input. The MagSafe identity and LED functions use the separate SYS_ONEWIRE path.
Diagnostic distinction: a green MagSafe LED does not prove that SMC_BC_ACOK, the charger SMBus, PPBUS_G3H regulation or SMC_PM_G2_EN is correct. Likewise, a valid ACOK signal does not prove that one-wire identification is working.
6. The SMC commands the 820-00165 PPBUS_G3H target
The charger controller can establish its approximately 8.1 V base PPBUS_G3H level before host adjustment. The SMC then communicates with U7100 through SMC_BC_SCL and SMC_BC_SDA and requests the normal charger-programmed target.
For 820-00165, the schematic specifies PPBUS_G3H at 8.6 V. The earlier 820-3437 example in the preceding guide is commonly measured near 8.45 V. This difference is model-specific, so 8.45 V should not be copied into the 820-00165 diagnostic target.
A rail that remains near 8.1 V is not the same as a missing PPBUS_G3H rail. Base-only operation suggests checking SMC power/reset state, SMC_BC_SCL/SDA activity, their pull-ups and U7100 response. A completely missing or very low rail requires the charger-stage and load-short diagnosis described in the preceding guide.
7. Battery SMBus, SYS_DETECT_L, AMON and BMON
The battery connector uses SMBUS_SMC_5_G3_SCL and SMBUS_SMC_5_G3_SDA to exchange battery status and charging information. These are SMBus signals, but they are not the same named bus as the SMC_BC_SCL/SDA pair used for U7100. The battery connector also provides SYS_DETECT_L.
AMON and BMON are analog monitor signals representing system-input and battery-charging current. They are measurements read by the SMC, not serial SMBus data lines.
8. SMC_PM_G2_EN enables the next standby-power stage
After its startup conditions are accepted, the SMC asserts SMC_PM_G2_EN toward U7501. This enables the following standby-power stage and allows the board to progress toward S5 and the later Intel CPU/PCH sequence.
Checkpoint: measure approximately 3.3 V on pin 1 of R8140. If the signal is missing, confirm the earlier SMC power, clock, reset, AVREF, ACOK and charger-control checkpoints before considering U5000 firmware or hardware.
Recommended SMC diagnostic order
| Order | Measure | Expected on 820-00165 | If missing or wrong |
|---|---|---|---|
| 1 | PP3V42_G3H | Approximately 3.42 V | Return to the always-on supply circuit and check for a shorted load. |
| 2 | PP3V3_S5_SMC_VDDA | Approximately 3.3 V | Check L5001, its source, local capacitors and resistance to ground. |
| 3 | PP1V2_S5_SMC_VDDC | 1.2 V | Check the model-specific 1.2 V source, enable path and load. |
| 4 | SMC_CLK32K | 32 kHz clock waveform | Check the clock source, routing and loading. |
| 5 | SMC_EXTAL/SMC_XTAL | 12 MHz oscillation | Check Y5110, R5110, C5110/C5111, supply rails and probe loading. |
| 6 | U5110 V+ and VIN | Valid PP3V42-level input; VIN above the 3.0 V threshold | Check R5127, input loading and PP3V42_G3H stability. |
| 7 | SMC_RESET_L | High, approximately 3.3 V | Check U5110, R5100, C5101, MR inputs and signal loading. |
| 8 | PP3V3_S5_AVREF_SMC | Approximately 3.3 V | Check U5110 REFOUT and the AVREF load. |
| 9 | SMC_BC_ACOK | High, approximately 3.3 V | Return to U7100 DCIN/VDD/ACIN validation and the pull-up path. |
| 10 | PPBUS_G3H at L7130 | About 8.1 V base, then approximately 8.6 V | Charger stage if absent; SMC/U7100 control if stuck near base. |
| 11 | SMC_BC_SCL and SMC_BC_SDA | Idle high with communication activity | Check pull-ups, shorts, U5000 state and U7100 response. |
| 12 | SMC_PM_G2_EN at R8140 | High, approximately 3.3 V | Check all earlier prerequisites and loading on the output. |
Four common SMC fault patterns
| What you see | What it usually means | Where to go next |
|---|---|---|
| SMC_RESET_L stays low although PP3V42_G3H is present | The supervisor has not accepted its inputs, reset is being forced, or the output is loaded. | Measure U5110 V+/VIN, MR1/MR2, R5100, C5101 and resistance on SMC_RESET_L. |
| Reset is high, but the 12 MHz or 32 kHz clock is missing | The SMC cannot execute reliably without the required clock source. | Check the correct clock circuit: Y5110 network for 12 MHz, or the separate SMC_CLK32K source. |
| PPBUS_G3H reaches approximately 8.1 V but not 8.6 V | The charger base regulator works, but SMC-commanded adjustment is absent or rejected. | Check SMC_BC_SCL/SDA, pull-ups, U5000 startup state and U7100 communication. |
| PPBUS_G3H is 8.6 V, but SMC_PM_G2_EN remains low | Some SMC functions are operating, but the next-state enable condition is not satisfied or the output is loaded. | Check signal loading, monitored conditions, SMC inputs and exact board-specific firmware before replacement. |
When should the SMC be replaced?
SMC replacement should be a late diagnostic step. First prove the supply rails, clocks, reset supervisor, AVREF, charger-valid input, relevant SMBus lines and the output load. A donor SMC must match the required board family and firmware configuration; identical package markings alone do not guarantee compatibility. Preserve the original SMC whenever its firmware can still be read or transferred.
Related Intel and Apple silicon repair guides
For the charger stage before SMC regulation, read Intel Mac power-on sequence: MagSafe to stable PPBUS_G3H. For the later CPU/PCH sleep-signal stage, continue to PM_SLP_S4_L timing and fault patterns. For newer designs, browse the Apple silicon Mac logic-board repair case studies.
Conclusion
A reliable SMC diagnosis follows the sequence rather than guessing from the final symptom: supply rails, clocks, reset, adapter-valid input, charger SMBus regulation and then SMC_PM_G2_EN. On 820-00165, correcting the PPBUS target to 8.6 V and separating the charger, battery and one-wire communication paths makes each failure pattern much easier to isolate.
