NAND Power and USB-C 20V Negotiation – A2442 820-02098
Last updated: 17 August 2026
Stage 5 of the A2442 M1 Pro power-on sequence begins after the embedded SMC has communicated with the NAND PMIC. UN400 then creates the 1.2V and 0.9V NAND supplies, enables UN480 to create the separate 2.5V rail, and releases the NAND devices from reset while the M1 Pro supplies their 24MHz clock.
In parallel, the embedded SMC communicates with the CD3217 USB-C port controllers. CD3217 negotiates a 20V USB-PD contract, PPDCIN_AON rises to approximately 20V, and U5200 ISL9240 changes from its initial boost operation to 20V-to-12V buck regulation.
This guide follows checkpoints 45–53 measured on a working 14-inch MacBook Pro A2442 logic board 820-02098. It separates NAND-power faults from USB-C negotiation faults because either branch can fail without proving that the other branch is defective.
Read the preceding embedded SMC and SoC ROM startup sequence, or return to the complete A2442 M1 Pro power-on sequence.
The measured times are working-board references, not universal pass-or-fail specifications. Charger, cable, battery, board configuration, temperature and capture trigger can change the observed timing.
Table of Contents
Where Stage 5 begins and ends
Stage 5 begins after I2C_NAND_PMIC_SDA_1V8 activity appears at approximately 4320ms. That Stage 4 transaction shows that the embedded SMC has reached the NAND power-management hand-off.
Stage 5 contains two parallel branches:
- NAND branch: UN400 creates PP1V2_NAND0 and PP0V9_NAND0, enables UN480 to create PP2V5_NAND0, then releases reset while the SoC supplies the NAND clock.
- USB-C and charger branch: CD3217 negotiates 20V, PPDCIN_AON rises to approximately 20V, and U5200 changes to buck mode while holding PPBUS_AON near 12V.
Stage 5 also includes PPVDD_AVEMSR_AWAKESW at approximately 4700ms. It ends when PPBUS_AON is stable at approximately 12.0V in buck mode around 5200ms. LCD, backlight and wireless enables begin in Stage 6.
Critical diagnostic rule: missing NAND or SSD power rails do not prevent the USB-C charger from negotiating 20V. Do not blame the NAND circuit merely because 20V is missing, and do not blame CD3217 merely because a NAND rail is absent.
Stage 5 sequence overview
Stage 5 prerequisites
Before diagnosing UN400 or UN480, confirm that the preceding embedded-SMC stage has completed and that the supply rails do not contain an abnormal short.
| Prerequisite | Expected condition | Why it matters |
|---|---|---|
| PMU_SYS_ALIVE | Approximately 1.8V high | Permits NAND, SSD and other later power paths |
| I2C_NAND_PMIC_SDA_1V8 / SCL | I²C waveform around 4320ms | Embedded SMC commands UN400 |
| PPVIN_P3V8NAND0_ISNS | Stable input supply | Main conversion input for UN400 |
| PP1V8_S2 | Approximately 1.8V | Supports detection, control and the NAND-PMIC interface |
| PPBUS_NAND0_ISNS | System-bus input present | High-voltage input path used by UN480 |
| NAND rail resistance | No abnormal short compared with a known-good board | Prevents UN400 or UN480 from entering protection |
How UN400 OCARINA controls NAND power
UN400 is the Apple NAND power-management IC identified by the schematic codename OCARINA. The schematic does not present OCARINA as an acronym, so it should be treated as a functional codename.
UN400 receives the 3.8V NAND input path, PMU_SYS_ALIVE and I²C commands from the embedded SMC. It then performs four jobs:
- Creates PP0V9_NAND0 with an internal buck converter.
- Creates PP1V2_NAND0 with a second internal buck converter.
- Asserts P2V5_NAND0_EN so UN480 can create PP2V5_NAND0.
- Controls NAND0_RESET_L and reports NAND power-good status.
Because PP0V9_NAND0 and PP1V2_NAND0 share UN400 and appear at the same measured time, losing both rails suggests a shared input, enable, I²C, PMU_SYS_ALIVE or UN400 fault. Losing only one rail directs attention to that output, its inductor, capacitors and downstream load.
PP1V2_NAND0 and PP0V9_NAND0
At approximately 4326ms, about 6ms after the NAND-PMIC I²C checkpoint, UN400 creates both core NAND supplies.
PP1V2_NAND0 at LN430
PP1V2_NAND0 reaches approximately 1.2V at LN430. This is UN400’s BUCK1 output. It powers the associated NAND and storage logic domains.
If PP0V9_NAND0 is present but PP1V2_NAND0 is missing, check resistance to ground, LN430 continuity, the output capacitors, UN400 BUCK1 switching and the NAND devices supplied by the 1.2V rail.
PP0V9_NAND0 at LN420
PP0V9_NAND0 reaches approximately 0.9V at LN420. This is UN400’s BUCK0 output.
If PP1V2_NAND0 is present but PP0V9_NAND0 is missing, check the PP0V9_NAND0 load, LN420 and its output-capacitor bank. A low resistance on a modern memory core rail is not automatically a short; compare the same model and configuration before condemning a NAND package.
P2V5_NAND0_EN and the UN480 2.5V regulator
UN400 does not directly create the 2.5V NAND rail. At approximately 4327ms it asserts P2V5_NAND0_EN to about 1.8V. RN488 is the practical checkpoint.
P2V5_NAND0_EN drives the enable input of UN480, a separate buck regulator. UN480 uses the NAND system-bus input and its local bias network, switches through LN480, and creates approximately 2.5V PP2V5_NAND0 at about 4328ms.
How to separate an UN400 enable fault from an UN480 power fault
| Measurement | Interpretation | Next checks |
|---|---|---|
| P2V5_NAND0_EN missing | UN400 has not requested the 2.5V rail | UN400 inputs, I²C, PMU_SYS_ALIVE, 0.9V/1.2V outputs and fault state |
| Enable present, PP2V5_NAND0 absent | The fault is downstream of the enable hand-off | UN480 input, bias, switching path, LN480 and PP2V5_NAND0 resistance |
| PP2V5_NAND0 pulses then collapses | Protection, unstable input or excessive output load | Scope UN480 switch node and compare rail resistance |
| PP2V5_NAND0 correct, NAND remains inactive | Move to reset, clock and NAND communication | NAND0_RESET_L and NAND0_CLK24M_R |
NAND reset and 24MHz clock
Correct supply voltages do not prove that the NAND devices can operate. They must also leave reset and receive a valid reference clock.
NAND0_RESET_L
NAND0_RESET_L should rise to approximately 1.2V and can be measured at TPU627. Because the signal is active low, a low level holds the NAND devices in reset and a high level releases them.
If all three NAND rails are stable but NAND0_RESET_L remains low, inspect UN400 power-good conditions, PMU_SYS_ALIVE, the reset line and any NAND-domain fault that prevents UN400 from releasing reset.
NAND0_CLK24M_R
The M1 Pro supplies a 24MHz clock through NAND0_CLK24M_R. TB_TP389 is the recorded practical point. The working-board table records a multimeter average near 0.67V, but that average is not proof of a 24MHz waveform.
Use a suitable high-impedance, low-capacitance oscilloscope probe. A missing clock with all rails and reset correct moves the diagnosis toward the SoC clock-output path, series components and NAND clock routing.
Why NAND power and 20V negotiation are separate branches
The NAND rails appear around 4326–4328ms, while PPDCIN_AON reaches 20V at approximately 4400ms. The measured reference explicitly notes that missing SSD power rails do not stop the 20V transition.
Both branches require the embedded SMC to progress through Stage 4, but their immediate owners differ:
| Branch | Immediate controller | Principal communication | Main output |
|---|---|---|---|
| NAND power | UN400 and UN480 | I2C_NAND_PMIC | 0.9V, 1.2V and 2.5V NAND rails |
| USB-C voltage negotiation | CD3217 | I2C_SMC_UPC plus USB-PD packets on CC | Approximately 20V PPDCIN_AON |
| System-bus conversion | U5200 ISL9240 | I2C_SMC_PWR and hardware regulation | Approximately 12.0V PPBUS_AON in buck mode |
How CD3217 negotiates the 20V input
At approximately 4230ms in Stage 4, the embedded SMC begins I2C_SMC_UPC communication with the CD3217 USB-C port controllers. CD3217 then performs the actual USB Power Delivery negotiation over the active CC pin.
- The USB-C charger is initially supplying approximately 5V.
- The embedded SMC communicates with CD3217 over I2C_SMC_UPC.
- CD3217 exchanges USB-PD messages with the charger over CC1 or CC2.
- The charger accepts the requested contract and raises VBUS to approximately 20V.
- The active CD3217 power path passes that voltage into PPDCIN_AON.
At approximately 4400ms, PPDCIN_AON reaches about 20V at FF200. U5200 does not transmit USB-PD packets. It receives and converts the voltage that CD3217 has already negotiated.
For the earlier firmware and CC sequence, see the CD3217 and ACE-ROM power-on sequence.
Diagnosing a missing 20V transition
If the initial 5V input and approximately 12.3V boost-mode PPBUS_AON are present but PPDCIN_AON never reaches 20V, work in this order:
- Confirm the charger and cable support the required USB-PD profile.
- Confirm Stage 4 I2C_SMC_UPC_SDA activity at RD190.
- Inspect the active CD3217 CC line for USB-PD BMC packet bursts.
- Verify the CD3217 ACE-ROM supply and SPI activity.
- Compare all USB-C ports; one damaged controller or port path may behave differently.
- Confirm that the negotiated VBUS reaches the board-side PPDCIN_AON path and FF200.
A basic CC voltage or 5V VBUS does not prove a successful USB-PD contract. Use an oscilloscope or PD analyser when the fault is beyond static attach detection.
PPVDD_AVEMSR_AWAKESW
At approximately 4700ms, U8100 MPMU system BUCK5 creates PPVDD_AVEMSR_AWAKESW at about 0.65V through L8253. This is a late SoC awake rail recorded between the 20V transition and final U5200 buck-mode checkpoint.
AVEMSR is an Apple internal domain name whose full expansion is not defined by this schematic. Retain the original rail name rather than inventing an expansion.
If this rail is missing while the NAND and 20V branches are correct, check U8100 BUCK5 prerequisites, L8253, the output-capacitor bank and the AVE/MSR domain resistance. Do not assume a low resistance on this 0.65V SoC rail is a short without a known-good comparison.
U5200 changes from boost mode to buck mode
Earlier in the sequence, the USB-C input is only 5V. U5200 operates Q5230, Q5240 and L5230 as a four-switch boost converter to create approximately 12.3V PPBUS_AON. That early boost is necessary to start the PMU and embedded SMC before the 20V contract exists.
After PPDCIN_AON rises to approximately 20V, the input is higher than the required system bus. U5200 therefore changes to buck mode:
- Q1 and Q2 inside Q5230 switch alternately.
- Q3 inside Q5240 remains off.
- Q4 inside Q5240 remains on.
- L5230 and the output capacitors smooth the PWM energy.
- PPBUS_AON settles near 12.0V at F5200 around 5200ms.
The change from approximately 12.3V to approximately 12.0V is normal. It is evidence of a mode change, not automatically a collapsing rail. For the complete converter and current-sense explanation, see the ISL9240 power-on sequence.
Complete measured Stage 5 order
| Step | Time | Signal or rail | Expected | Test point | Meaning | If missing |
|---|---|---|---|---|---|---|
| 45 | 4326ms | PP1V2_NAND0 | ≈1.2V | LN430 | UN400 creates the NAND 1.2V rail after SYS_ALIVE and I²C | NAND / SSD power incomplete |
| 46 | 4326ms | PP0V9_NAND0 | ≈0.9V | LN420 | UN400 creates the NAND 0.9V rail | NAND / SSD power incomplete |
| 47 | 4327ms | P2V5_NAND0_EN | ≈1.8V | RN488 | UN400 enables UN480 | No PP2V5_NAND0 request |
| 48 | 4328ms | PP2V5_NAND0 | ≈2.5V | LN480 | UN480 creates the NAND 2.5V rail | NAND / SSD power incomplete |
| 49 | After rails | NAND0_RESET_L | ≈1.2V high | TPU627 | UN400 releases NAND reset | NAND devices remain in reset |
| 50 | After rails | NAND0_CLK24M_R | 24MHz waveform; DC average ≈0.67V | TB_TP389 | M1 Pro supplies the NAND reference clock | NAND clock path missing |
| 51 | 4400ms | PPDCIN_AON | ≈20V | FF200 | CD3217 and the charger complete the higher-voltage USB-PD contract | Check I2C_SMC_UPC, ACE-ROM, CD3217, CC and charger |
| 52 | 4700ms | PPVDD_AVEMSR_AWAKESW | ≈0.65V | L8253 | U8100 BUCK5 creates the AVE/MSR awake rail | MPMU BUCK5 or AVE/MSR load fault |
| 53 | 5200ms | PPBUS_AON | ≈12.0V | F5200 | U5200 changes to 20V-input buck regulation | Buck-mode converter stage missing or unstable |
Rail and signal ownership
| Missing checkpoint | Primary owner | First checks |
|---|---|---|
| PP1V2_NAND0 / PP0V9_NAND0 | UN400 OCARINA | Input supply, PMU_SYS_ALIVE, I²C, rail resistance and inductors |
| P2V5_NAND0_EN | UN400 OCARINA | UN400 state, 0.9V/1.2V rails and fault conditions |
| PP2V5_NAND0 | UN480 | Enable, input, bias, LN480 and output load |
| NAND0_RESET_L | UN400 OCARINA | Power-good, SYS_ALIVE, reset routing and NAND faults |
| NAND0_CLK24M_R | M1 Pro SoC | Clock source, routing, series components and SoC state |
| 20V PPDCIN_AON | CD3217 plus USB-C charger | I2C_SMC_UPC, ACE-ROM, CC traffic, port and cable |
| PPVDD_AVEMSR_AWAKESW | U8100 MPMU BUCK5 | U8100 prerequisites, L8253 and rail load |
| 12.0V buck-mode PPBUS_AON | U5200, Q5230 and Q5240 | 20V input, I²C_SMC_PWR, gate drive, sense paths and system load |
Recommended diagnostic order
- Confirm Stage 4 I2C_NAND_PMIC activity and PMU_SYS_ALIVE.
- With all power removed, compare PP1V2_NAND0, PP0V9_NAND0 and PP2V5_NAND0 resistance with a known-good board.
- Measure PP1V2_NAND0 at LN430 and PP0V9_NAND0 at LN420.
- Measure P2V5_NAND0_EN at RN488.
- If the enable is present, measure PP2V5_NAND0 at LN480 and inspect UN480 switching.
- Confirm NAND0_RESET_L rises high at TPU627.
- Use an oscilloscope to verify NAND0_CLK24M_R at TB_TP389.
- Independently confirm I2C_SMC_UPC activity and USB-PD traffic.
- Measure PPDCIN_AON at FF200 for the 5V-to-20V transition.
- Measure PPVDD_AVEMSR_AWAKESW at L8253.
- Confirm PPBUS_AON changes from approximately 12.3V boost mode to approximately 12.0V buck mode.
- Stop at the last confirmed checkpoint and diagnose its immediate owner.
Common Stage 5 fault patterns
| What you observe | Most useful interpretation |
|---|---|
| No 0.9V and no 1.2V NAND rails | Shared UN400 input, I²C, PMU_SYS_ALIVE, PMIC or common load fault |
| Only one UN400 rail is missing | Individual buck channel, inductor, capacitor bank or downstream rail fault |
| 0.9V and 1.2V correct but P2V5_NAND0_EN missing | UN400 has not released the external 2.5V stage |
| 2.5V enable present but PP2V5_NAND0 missing | UN480 input, bias, switching stage, LN480 or output-load fault |
| All NAND rails present but reset remains low | UN400 power-good, reset-control or NAND-domain fault |
| Rails and reset correct but no 24MHz clock | SoC clock-output or clock-routing fault |
| NAND rails missing but PPDCIN_AON reaches 20V | Expected branch independence; remain with UN400/UN480 diagnosis |
| NAND rails correct but PPDCIN_AON remains at 5V | I2C_SMC_UPC, CD3217, ACE-ROM, CC, charger or cable fault |
| PPDCIN_AON reaches 20V but PPBUS_AON is unstable | U5200 buck-mode, Q5230/Q5240, L5230, sensing or system-load fault |
| PPBUS_AON changes from 12.3V to 12.0V and stays stable | Normal transition from initial boost to later buck mode |
Terminology used in this guide
| Term | Full name or meaning | Function in Stage 5 |
|---|---|---|
| NAND | Not AND flash memory | Non-volatile storage used for the Mac’s internal data |
| PMIC | Power Management Integrated Circuit | Creates and sequences multiple supply rails |
| OCARINA | Apple functional codename | UN400 NAND PMIC |
| BUCK0 / BUCK1 | Internal step-down regulator channels | Create PP0V9_NAND0 and PP1V2_NAND0 |
| USB-PD | USB Power Delivery | Protocol used by CD3217 and the charger to negotiate 20V |
| CC1 / CC2 | Configuration Channel 1 / 2 | USB-C attach, orientation and USB-PD communication path |
| VBUS | USB bus power | Charger voltage that changes from 5V to 20V |
| PPDCIN_AON | Always-on DC input rail | Negotiated USB-C voltage passed into the charger circuit |
| PPBUS_AON | Always-on system bus | Approximately 12V system supply regulated by U5200 |
| Buck | Step-down voltage conversion | Reduces the later 20V input to approximately 12V |
| Boost | Step-up voltage conversion | Raises the initial 5V input to approximately 12.3V |
| I²C | Inter-Integrated Circuit | Management communication with UN400, CD3217 and U5200 |
| SDA | Serial Data | Bidirectional I²C data line |
| SCL | Serial Clock | I²C clock line |
| RESET_L | Reset, active low | Low holds NAND in reset; high releases it |
| PGOOD | Power Good | Reports that a regulator output is within its valid range |
| AON | Always On | Rail required during the early and persistent power states |
| AVEMSR | Apple internal domain name; expansion not defined here | Late MPMU awake rail produced by BUCK5 |
Frequently asked questions
Can the Mac negotiate 20V if the NAND rails are missing?
Yes. The working-board notes explicitly separate the NAND-power path from the CD3217 USB-PD path. Missing SSD power does not by itself prevent PPDCIN_AON from reaching 20V.
Does U5200 ISL9240 negotiate 20V?
No. CD3217 exchanges USB-PD packets with the charger. U5200 converts the voltage that CD3217 passes into PPDCIN_AON.
Why does PPBUS_AON fall from about 12.3V to about 12.0V?
The early 12.3V value is produced while U5200 boosts from a 5V input. After the input becomes 20V, U5200 changes to buck mode and regulates PPBUS_AON near 12.0V.
Do correct NAND voltages prove that the NAND is working?
No. The devices also need NAND0_RESET_L high, a valid 24MHz clock and correct data communication. Correct rails prove only the power portion of the sequence.
Is a low resistance on PP0V9_NAND0 automatically a short?
No. Low-voltage memory and SoC rails can have naturally low resistance. Compare with a known-good A2442 board using the same memory configuration before making a decision.
Can I test the NAND clock with a multimeter?
A multimeter may show the reference average near 0.67V, but it cannot prove a 24MHz waveform. Use an appropriate oscilloscope probe.
Measurement and safety notes
Use DC voltage measurements for the NAND rails, P2V5_NAND0_EN, NAND0_RESET_L, PPDCIN_AON, PPVDD_AVEMSR_AWAKESW and PPBUS_AON. Use an oscilloscope or logic analyser for I²C, the NAND clock, USB-PD traffic and switching-node diagnosis.
Disconnect all power before resistance, continuity or diode-mode testing. Use a fine probe and board support to avoid slipping between densely spaced NAND and PMIC components.
Do not inject an assumed voltage into a NAND rail or communication line. These rails are tightly sequenced and directly connected to storage devices containing customer data. Back up readable ROM or configuration data before replacing or reprogramming any storage-control component.
Never connect a grounded oscilloscope clip to a floating charger switch node. An incorrect ground connection can damage U5200, Q5230, Q5240 or the logic board.
Continue to Stage 6
After PPBUS_AON is stable in buck mode, the measured sequence continues with LCD_PWR_EN, BL_PMIC_PWR_EN, PP1V2_AWAKESW_BLC, BL_PWR_EN, display identification and later wireless enables. Return to the complete A2442 820-02098 M1 Pro power-on sequence and continue with Stage 6.
