A2159 820-01598 Power-On Sequence

Summary

The 2019 13-inch MacBook Pro A2159 does not move directly from a 5V USB-C input to a running Intel CPU. U7000 first creates the main system bus, U7800 Calpe-L powers the T2/embedded-SMC system, the T2 reads its external ROM and communicates with the charger and CD3217 controllers, and only then are the main standby and NAND rails released.

After this adapter-insertion sequence, the board waits for a power-button event. The second sequence brings up the Intel CPU/PCH deep-sleep, memory, VCCIO and IMVP rails before releasing resets and enabling the internal display and backlight. Finding the first missing or withdrawn event is much more reliable than diagnosing from USB-C current alone.

Two timing baselines are used on this page. Table A uses VBUS = 5V at adapter connection as 0ms. Table B restarts the clock at the active-low PMU_ONOFF_L power-button event. Do not add the Table B times directly to the Table A times.

Evidence boundary: absolute millisecond values come from the supplied measured A2159 sequence. Rail ownership and the formal order are checked against the 820-01598 schematic. Exact times vary with charger, board state, battery state, firmware and oscilloscope trigger placement; use them as a known-good diagnostic reference rather than universal pass/fail limits.

How to use this power-on sequence

Start with stable rails

Use a multimeter for DC rails such as PPBUS_G3H, PP3V3_G3H_RTC and PP5V_G3S. Check resistance or diode mode only with all power removed. A shorted downstream rail can make the correct enable appear briefly and then collapse.

Use a scope for activity

Clocks, SPI, I2C, SPMI and short active-low resets cannot be proved with a DC reading. Confirm oscillation or transactions at the named resistor or pad and compare the first failed edge with the immediately preceding rail.

Follow the first missing event

If a later rail is absent, do not jump straight to its regulator. Work backward to its enable, power-good input, upstream supply and controlling device. The earliest abnormal event is normally closest to the cause.

Watch for deliberate pulses

PPVCC_S0_CPU changes voltage after VID communication, and PPVCCGT_S0_CPU may pulse and return to 0V. A changing rail is not automatically faulty; correlate it with reset, power-good and shutdown timing.

Circuit ownership

Component	Identity	Sequence role	Key inputs	Key outputs
U3100 / U3200	CD3217 ACE2 USB-C controllers	Control the two USB-C VBUS paths, CC/USB-PD communication and access to the shared TBT/ACE ROM. The measured `PP3V3_UPC_XB_LDO` and `UPC_XB_SPI_CS_L` checkpoints belong to the XB/U3200 branch.	5V VBUS, `PP3V3_G3H_RTC`, resets and T2 I2C commands	`PPDCIN_G3H`, internal 3.3V LDO, SPI-ROM access and negotiated 20V VBUS
U2890	TBT-X / ACE firmware ROM	Stores firmware used by the CD3217/Thunderbolt subsystem. SPI chip-select activity from the XB controller is an early proof that the controller is powered and attempting firmware access.	`PP3V3_UPC_XB_LDO`, SPI clock and chip select	SPI MISO firmware data
U7000	ISL9240 charger	Creates its internal VDDP/VDDA bias, operates in boost mode from the initial 5V input to create about 12.3V `PPBUS_G3H`, and later changes to buck mode after 20V USB-PD negotiation.	`PPDCIN_G3H`, `CHGR_AUX_DET`, I2C power-bus commands	`PPBUS_G3H`, `CHGR_EN_MVR` and charger status
U6903	Early MVR regulator	Uses `CHGR_EN_MVR` to create `PP3V3_G3H_RTC`, the early 3.3V rail required by U7800, the CD3217 controllers and other always-on devices.	`PPBUS_G3H`, `CHGR_EN_MVR`	`PP3V3_G3H_RTC`
U7800	338S00466 Calpe-L PMU	Central power-management controller. It creates T2 awake rails, clocks, resets, early CPU/PCH rails and, on the 2-NAND configuration, the direct 0.9V and VCCQ NAND supplies.	`PP3V3_G3H_RTC`, PMU crystal, PBUS sense, T2 SPMI and I2C	SLPS2R/AWAKE rails, `PMU_SYS_ALIVE`, `PMU_PVDDMAIN_EN`, S5/S3 rails and NAND enables
U3900	T2 SoC / embedded SMC	Receives the Calpe rails and clocks, reads U4770, communicates with CD3217 and the power system, monitors the power button, coordinates eSPI with the Intel PCH and directs later power-state transitions.	SLPS2R/AWAKE rails, 32kHz and 24MHz clocks, reset, external ROM	I2C, SPMI, `PM_RSMRST_L`, power-button/PCH control and system policy
U4770	T2 external SoC ROM	Read by U3900 after `PMU_SYS_ALIVE` and reset release. SPI activity around 1880ms proves the T2 has progressed beyond basic power and clock startup.	`PP1V8_AWAKE`, SPI CS/CLK/MOSI	SPI MISO boot data
U7650	Main 3V/5V standby regulator	Enabled by `PMU_PVDDMAIN_EN`. It takes over the main 3.3V path and creates `PP5V_G3S`; its power-good outputs allow the PCH RTC and G3S branches to continue.	`PPBUS_G3H`, `PMU_PVDDMAIN_EN`	`PP3V3_G3H`, `PP5V_G3S`, main power-good signals
U8200 / U8220	G3S regulators	Create the secondary 3.3V and 1.8V G3S rails after the 3V/5V standby stage is valid.	`PP3V3_G3H_RTC`, `PP1V8_SLPS2R` and enables	`PP3V3_G3S`, `PP1V8_G3S`
U9080	TPS62180 NAND regulator	Creates the 2.5V NAND supply from `PPBUS_G3H_SSD0` and reports power good before NAND reset release.	`SSD0_VR_P2V5_EN`, `PPBUS_G3H_SSD0`	`PP2V5_NAND_SSD0`, `SSD0_VR_P2V5_PGOOD`
U8110 / U7100	VCCIO regulator / Intel IMVP controller	U8110 creates CPU VCCIO and its power good. `ALL_SYS_PWRGD` then enables U7100 and the CPU core, system-agent and graphics regulators.	S3/S0 enables, main standby rails and PCH sequencing	`PPVCCIO_S0_CPU`, CPU core/SA/GT rails and `CPU_VR_READY`
U0500 / U8400	Intel CPU-PCH / LCD backlight driver	U0500 releases the late platform and display signals after CPU/PCH power-good sequencing. U8400 receives `EDP_BKLT_EN` and controls the LCD backlight boost stage.	CPU rails, resets, HPD and panel state	Platform reset, display power request and backlight operation

Power-on sequence diagram Part 1: USB-C input, T2 and NAND startup

This diagram maps the first timing baseline, beginning when the charger supplies 5V VBUS. Follow the blue numbered markers from the active USB-C/CD3217 path through U7000 ISL9240, the early 3.3V rail, U7800 Calpe PMU and the T2 awake domains. The later markers show T2 ROM access, power-management communication, USB-PD negotiation to 20V, the main G3S standby rails and the two-NAND power branch.

How to read Part 1

The upper section covers CD3217 VBUS pass-through, U2890 firmware access and U7000 boost/buck operation.
The lower section follows Calpe PMU self-start, T2 rails, clocks, reset, SPMI and external SoC-ROM activity.
The NAND branch shown is the measured two-NAND implementation. Confirm the fitted SSD topology before applying it to a four-NAND board.

A2159 820-01598 power-on sequence part 1 showing CD3217 USB-C input, ISL9240 charger, U7800 Calpe PMU, T2 awake rails, SoC ROM and NAND power — A2159 board 820-01598 power-on sequence Part 1: USB-C input, CD3217 firmware access, ISL9240 boost and buck operation, Calpe PMU startup, T2 awake rails and NAND power.

Tip: open the image in a new browser tab when you need to zoom into component designators or signal names, then return to Table A for the measured time, expected value and fault-isolation guidance.

Table A: adapter insertion, T2 startup, 20V and NAND

Baseline A: VBUS = 5V at 0ms

Step	Time	Signal / Rail	Expected	Test Point	Meaning	If Missing
A1 - USB-C input and charger boost startup
A01	0ms	`VBUS`	5V	C3101, connector side of CD3217 pass FET	The charger presents initial USB-C VBUS before the CD3217 internal high-voltage path.	Check charger, cable, USB-C connector, CC pins and shorted VBUS input components before board-level sequencing.
A02	0ms	`PPDCIN_G3H`	5V	F3000	Confirms a CD3217 has passed the initial VBUS into the board and U7000 receives approximately 5V at P_IN.	If VBUS is present before CD3217 but absent here, inspect the active port controller, its internal pass path, reset/power and PPDCIN loading.
A03	80ms	`CHGR_VDDP`	About 5.1V	R7075	U7000 has created its VDDP bias; this supports VDDA and charger configuration including CELL selection.	Verify PPDCIN at U7000, bias capacitors, U7000 soldering and shorts on VDDP/VDDA.
A04	Early	`CHGR_AUX_DET`	About 1.3V on 5V input; threshold above 1.05V	R7016	U7000 confirms PPDCIN is above approximately 4V and is allowed to continue into boost operation.	If below threshold, verify divider components, PPDCIN stability and leakage. U7000 can stop before PPBUS boost even when 5V is visible elsewhere.
A05	200ms	`PPBUS_G3H`	About 12.3V	F7000	U7000 is operating in boost mode from the 5V input. This is the main system/battery bus.	Check `CHGR_AUX_DET`, U7000 switching nodes, current-sense paths, F7000 and resistance on PPBUS. Do not inject voltage until the shorted branch is identified.
A06	350ms	`PP3V3_G3H_RTC`	3.3V	L6900	U7000 has asserted `CHGR_EN_MVR`; U6903 creates the early 3.3V rail for U7800, both CD3217s, MESA/Touch ID and other always-on devices.	Check `CHGR_EN_MVR`, U6903 input/output, L6900 and rail resistance. Without this rail, PMU and USB-C firmware activity cannot progress.
A2 - CD3217 firmware access and Calpe-L self-start
A07	390ms	`PP3V3_UPC_XB_LDO`	3.3V	C2890 / U2890 supply	The XB CD3217 U3200 internal LDO powers the shared TBT-X/ACE ROM and SPI/I2C pull-ups. The supplied notes state the XA LDO branch is not used for this ROM supply.	Check U3200 input power, reset, LDO loading and U2890 supply decoupling.
A08	400-550ms	`UPC_XB_SPI_CS_L` / `TBT_X_SPI_CS_L`	Active-low SPI chip-select pulses	R3096 / U2890 CS path	U3200 attempts to read U2890. This firmware access is normally required before full USB-PD negotiation.	Check the 3.3V LDO, CS/CLK/MOSI/MISO continuity and U2890. Before reflashing, prove power, chip select, clock and data integrity.
A09	Before PMU rails	`VIN_RTC` and `PMU_VDD_HI`	`VIN_RTC > 3V`; `PMU_VDD_HI > 2.15V`; source notes PBUS > 7.49V	U7800 supply/sense nodes	These are Calpe-L start conditions. U7800 will not release its internal sequence until both early 3.3V and bus-voltage conditions are valid.	Return to `PP3V3_G3H_RTC` and `PPBUS_G3H`; inspect sense-divider accuracy and PMU input loading.
A10	Early	`PMU_XTAL`	Sine-wave oscillation at Y8001	Y8001 pins 1 and 2	Provides the Calpe-L timebase. DC bias values alone do not prove oscillation.	Use a high-impedance scope probe. Check Y8001, load capacitors, U7800 power and physical damage. The source lists inconsistent pin-1 DC bias values, so waveform presence is the reliable test.
A11	410ms	`PP3V3_G3H_PMU_VDDMAIN`	3.3V	L7690	`PP3V3_G3H_RTC` passes through an internal U7800 FET to VDD_MAIN_S/W/E/N, self-powering Calpe Buck 0-8 control circuits before U7650 takes over the main rail.	If RTC 3.3V is present but VDDMAIN is absent, inspect U7800, its internal-gate prerequisites and shorts on the PMU main-supply domain.
A3 - T2 awake rails, clocks, reset and external ROM
A12	1687ms	`PP1V8_SLPS2R`	1.8V	L7813	First major Calpe rail for U3900 T2 VDD/VDDIO and associated always-on control, including SOC_FORCE_DFU and LID_OPEN pull-ups.	Check U7800 input/VDDMAIN, L7813, rail resistance and whether the PMU is repeatedly restarting.
A13	1688ms	`PMU_CLK32K_SOC`	32.768kHz clock; source DC bias about 0.863V	R8011	U7800 supplies the T2 32kHz reference. SPMI communication is not expected to operate correctly without it.	Scope the waveform at R8011. Check U7800 clock output and loading toward U3900.
A14	Same awake burst; exact time not recorded	`PP1V8_AWAKE`	1.8V	R4770	Powers T2 VDDIO, U4770 SoC ROM VCC and SEP EEPROM VCC.	Check U7800 BUCK3_SW1 output, R4770 path and shorts at the ROM/SEP/T2 loads.
A15	1689ms	`PP1V1_SLPS2R`	1.1V	L7814	Supplies a T2 core domain and feeds the later `PP1V1_SLPDDR` conversion.	Check L7814 and load resistance. A short here can abort the entire awake sequence.
A16	1690ms	`PP0V8_SLPS2R`	0.8V	C7905	U7800 LDO0 powers the T2 VDD_LOW domain.	Inspect U7800 LDO0 output and the T2 low-voltage load. Use diode mode comparison before suspecting U3900.
A17	Same awake burst; exact time not recorded	`PP0V82_SLPDDR`	0.82V	L7811	Additional T2 sleep-to-running/DDR-related VDD rail.	Check L7811, upstream Calpe output and rail resistance.
A18	1691ms	`PP3V3_AWAKE`	3.3V	C4595	U7800 V3P3_SW1 powers the T2 VDD33_USB domain and awake pull-ups.	Check U7800 V3P3_SW1 and 3.3V awake consumers for a short or excessive load.
A19	1692ms	`PPVDDCPUSRAM_AWAKE`	Approximately 0.8-1.06V	L7810	Calpe supplies T2 CPU SRAM power.	Check L7810 switching and rail resistance. A low normal resistance is not alone proof of a short; compare voltage and current behaviour.
A20	1693ms	`PP0V9_SLPDDR`	0.9V	L7816	Powers T2 fixed-voltage, CPU-fixed, PCIe and USB domains.	Check L7816, the associated Calpe buck and downstream T2/PCIe loading.
A21	1694ms	`PP1V1_SLPDDR`	1.1V	L4590	U7901 converts `PP1V1_SLPS2R` for T2 DDR I/O, reference and crystal-related domains.	If the input rail is present, check U7901 enable/output and shorts on the 1.1V SLPDDR domain.
A22	1696ms	`SOC_XTAL24M_OUT` / `IN`	24MHz sine waves; source DC bias about 0.527/0.547V	R3940 pins 1 and 2 / Y3940	U3900 now has its 24MHz reference, powered from the 1.1V SLPDDR domain.	Use a scope, not a DC reading. Check Y3940, R3940 paths, `PP1V1_SLPDDR` and U3900 loading.
A23	1698ms	`PP1V2_AWAKE`	1.2V	C7914	U7800 LDO2 powers T2 CPU_UVD, PCIe and PLL domains.	Check LDO2 output loading and T2-related consumers.
A24	1699ms	`PPVDDCPU_AWAKE`	Approximately 0.625-1.06V	L7806, L7807, L7808 and L7809	Main T2 CPU awake supply. Multiple inductors distribute the high-current domain.	Check all phases/inductors, enable state and whether the rail rises then collapses because of missing SPMI or a load fault.
A25	1700ms	`PMU_SYS_ALIVE`	1.8V high	R9610	U7800 declares the PMU sequence valid to T2 and participates in the SSD PFN path.	Confirm every preceding Calpe rail and clock. If rails are present but SYS_ALIVE is absent, check PMU reset, oscillator and internal sequencing conditions.
A26	1700ms	`PMU_ACTIVE_READY`	1.8V high	RE027	Calpe ACTIVE_RDY handoff to T2 and the USB-C controller logic.	Check the same prerequisites as SYS_ALIVE and continuity toward U3900/U3100.
A27	1700ms	`PMU_COLD_RESET_L`	1.8V high after release	R4039	Active-low cold reset is released to T2, including its CFSB_AON/reset domain.	If held low, locate the controller holding reset and verify T2 supplies, clocks and PMU status before replacing U3900.
A28	After awake rails	`SPMI_DATA` / `AON_SPMI_SDATA`	Bidirectional transaction activity	U7800-T2 SPMI data path	T2 and Calpe exchange power-management commands. The measured note reports that failed communication can make U7800-created rails drop after about 1000ms and restart while VBUS remains 5V.	Scope both SPMI data and clock. Verify 32kHz, T2 reset and all awake rails. Repeating rail cycles are a symptom, not proof that U7800 itself is bad.
A29	1880ms	`SPI_SOCROM_CS_L`, CLK, MOSI, MISO	SPI activity	U4770	U3900 T2 reads its external SoC ROM. This proves T2 power, clocks and reset have progressed into ROM execution.	Check `PP1V8_AWAKE`, U4770 power, CS/CLK continuity and MISO. Compare with a known-good capture before programming or replacing the ROM.
A30	2460ms	`I2C_UPC_SDA`	Approximately 1.6-1.8V data transitions, then traffic may stop	R3045	T2 communicates with the CD3217/UPC subsystem. This branch is required for later USB-PD 20V negotiation.	Check pull-ups, both CD3217 supplies/resets, U2890 firmware access and SCL. A stuck-low line identifies a bus or device fault; an idle-high line is not proof of communication.
A31	2460ms	`I2C_PWR_SDA`	Continuing 1.6-1.8V data transitions	R5283	T2 communicates with U7000 charger and U7800 power management.	Check SCL, pull-ups, U7000/U7800 power and bus loading. Missing power-bus communication can prevent both 20V negotiation and `PMU_PVDDMAIN_EN`.
A4 - 20V USB-PD negotiation and main G3S standby rails
A32	2500ms	`VBUS`	20V on the active port	C3101, connector side	The CD3217 and charger have completed USB-PD negotiation with a compatible supply.	If both I2C buses are active but VBUS stays at 5V, verify CC traffic, charger/cable capability, the active CD3217, U2890 SPI read and firmware integrity. Do not flash U2890 before proving its electrical interface.
A33	After 20V	`CHGR_AUX_DET`	About 5.1V	R7016	U7000 detects the higher valid input and changes from boost operation to buck regulation.	Check the AUX_DET divider and confirm 20V reaches the U7000 input side.
A34	3500ms	`PPBUS_G3H`	About 12.6V	F7000	U7000 now regulates PPBUS in buck mode from 20V. A small difference from the earlier 12.3V boost value is normal in this capture.	If 20V is present but PPBUS is wrong, inspect U7000 buck switching, current sense, battery interaction and PPBUS loading.
A35	3520ms	`PMU_PVDDMAIN_EN`	3.3V high	R7660	U7800 VR_EN enables U7650 through `P5VXX_EN`, starting the main 3V/5V standby stage.	Check T2/PMU communications and all prior awake milestones. If enable is high, move to U7650 input, switching and output checks.
A36	Immediately after enable	`PP3V3_G3H`	3.3V	L7690	U7650 takes over the main 3.3V path previously self-powered through the Calpe VDDMAIN path and supplies later S4/S3/S0 loads.	Check U7650, its enable and the 3.3V load. A collapse during handover can look like a PMU reset.
A37	3536ms	`P3V3MAIN_PGOOD`	3.3V high	R7601	Confirms the main 3.3V output is within regulation.	If PP3V3_G3H is correct but PGOOD is low, check feedback/ripple, the PGOOD pull-up and U7650. If the rail is low, diagnose the supply first.
A38	3537ms	`PP3V_G3H_RTC`	3.0V	R1401	U7800 LDO1 supplies the Intel CPU/PCH RTC-only domain, including VCCRTC and intrusion-related logic.	Check LDO1, its power-good prerequisite and RTC-domain resistance at U0500.
A39	3537ms	`PMU_CLK32K_PCH`	32.768kHz sine/square-like clock; source DC bias about 0.861V	R8012	U7800 provides the PCH RTC clock at RTCX1.	Scope R8012. Without this clock, RTC reset and PCH deep-sleep progression can stop.
A40	3557ms	`PCH_RTC_RESET_L`	3.0V high after release	No dedicated measurement point listed	U7800 LDO1_POK releases the Intel RTCRST/SRTCRST RTC reset domain.	Measure at an accessible series/pull-up point if available. Verify 3.0V RTC power and 32kHz clock first.
A41	Before 3558ms	`P5VG3S_EN`	High enable	U7650 enable path	Requests the 5V G3S output.	Check the delayed enable network and U7650 prerequisites.
A42	3558ms	`PP5V_G3S`	5V	L7670	U7650 creates the main 5V standby rail used by multiple S0 regulators and peripherals.	Check U7650 switching, L7670 and shorts on PP5V_G3S.
A43	3558.2ms	`PP3V3_G3S`	3.3V	C8200	U8200 creates the G3S 3.3V branch.	Verify its input, enable and output loading.
A44	Same G3S burst; exact time not recorded	`PP1V8_G3S`	1.8V	C8220	U8220 converts `PP1V8_SLPS2R` into the 1.8V G3S rail.	Check the still-present SLPS2R input, U8220 enable and G3S load.
A45	3558.6ms	`P5VG3S_PGOOD`	High	U7650 PGOOD path	Confirms the 5V G3S regulator is stable.	Check PP5V_G3S level/ripple, feedback and PGOOD pull-up.
A46	3559ms	`PMU_CLK32K_WLANBT`	32.768kHz clock; source DC bias about 0.141V	R8016	U7800 provides the Wi-Fi/Bluetooth reference clock.	Scope R8016; a low DC average can be normal for a clock. Check clock output/loading rather than judging by DC voltage alone.
A5 - 2-NAND SSD power branch
A47	Before SSD rails	`SSD topology decision`	Confirm 2-NAND Calpe or 4-NAND OCARINA implementation	Inspect fitted NAND landing and U9000 population	The updated sequence explicitly separates the two SSD power architectures. On the measured 2-NAND board, U7800 Bucks 9 and 10 create the 0.9V and VCCQ rails. Four-NAND boards use OCARINA U9000 and `SSD_PMU_RESET_L`.	Do not continue with the wrong branch. Confirm the fitted hardware before diagnosing missing NAND rails, enables or reset.
A48	3618ms	`PPVCCQ_ANI_SSD0`	1.8V on this measured 2-NAND option; some NAND options use 1.2V	L7824	U7800 Buck 10 directly supplies NAND VCCQ/ANI on the 2-landing configuration.	Confirm the board NAND option, then check U7800 Buck 10, L7824 and NAND-rail resistance. Do not apply the 4-landing OCARINA diagnosis to this variant.
A49	3619ms	`PP0V9_SSD0`	0.9V	L7823	U7800 Buck 9 directly supplies the NAND 0.9V rail on the 2-landing configuration.	Check L7823, Buck 9 switching and all NAND loads. The original note incorrectly repeated L7824 in the path; the schematic confirms L7823.
A50	3620ms	`SSD0_PMIC_VR_P2V5_EN` / `SSD0_VR_P2V5_EN`	Enable high	U9080 enable path	U7800 requests U9080 to create the NAND 2.5V supply.	Check the enable source, level, U9080 input `PPBUS_G3H_SSD0` and pull networks.
A51	3628ms	`PP2V5_NAND_SSD0`	2.5V	L9080	U9080 TPS62180 has produced the NAND high-voltage rail from PPBUS.	Check U9080, L9080, output capacitors and NAND-rail resistance.
A52	After 2.5V is stable	`SSD0_VR_P2V5_PGOOD`	1.8V high	R9088	U9080 reports valid 2.5V regulation to U7800.	If 2.5V is correct, check the PGOOD output/pull-up and continuity to U7800. If 2.5V is wrong, diagnose the regulator first.
A53	3630ms	`SSD0_PMIC_RESET_L`	1.8V high after release	R9615	U7800 releases `SSD0_RESET_L` to the two NAND packages only after the NAND supplies are valid.	Verify 0.9V, VCCQ, 2.5V and PGOOD. A held-low reset can be correct when any NAND rail is missing.

SSD configuration warning: the schematic supports both 2-landing and 4-landing SSD implementations. On the 2-landing option shown in the measured sequence, Calpe U7800 creates PP0V9_SSD0 and PPVCCQ_ANI_SSD0 directly. On a 4-landing implementation, OCARINA U9000 and SSD_PMU_RESET_L control those rails. Confirm the fitted configuration before fault isolation.

Power-on sequence diagram Part 2: power button, Intel CPU and display

Part 2 begins with a new timing reference at the active-low PMU_ONOFF_L event. It shows how U7800 releases the Intel S5 and S3 supplies, how eSPI communication allows the PCH to advance its sleep states, and how U8110 and U7100 bring up the CPU VCCIO and IMVP rails before platform reset, panel power and backlight enable.

How to read Part 2

Start at SE030 and verify the S5 rails before expecting PCH power-button and resume-reset hand-offs.
eSPI reset, chip-select, 60MHz clock and data-lane activity must occur before the S3 memory and S0 support rails can follow.
PPVCCIO_S0_CPU and its power-good precede ALL_SYS_PWRGD, CPU core/system-agent/graphics power and the late display sequence.

A2159 820-01598 power-on sequence part 2 showing PMU_ONOFF_L, S5 and S3 rails, PPVCCIO_S0_CPU, Intel CPU power, display and backlight enables — A2159 board 820-01598 power-on sequence Part 2: power-button request, Intel S5 and S3 rails, CPU VCCIO and IMVP power, platform reset, internal display and backlight enables.

Tip: the diagram shows circuit ownership and signal flow; use Table B for the revised millisecond timing, including PPVCCIO_S0_CPU at 280.2ms.

Table B: power-button event, S5-S0, CPU and display

Baseline B: PMU_ONOFF_L active-low event = 0ms

Step	Time	Signal / Rail	Expected	Test Point	Meaning	If Missing
B1 - Power-button request, S5 rails and eSPI link training
B01	0ms	`PMU_ONOFF_L`	Active-low pulse/event	SE030 pad	Starts the second timing baseline after the SMC begins power-button monitoring. The supplied A2159 bench sequence waits for this event instead of continuing automatically.	Confirm Table A completed, then verify the top-case/power-button path or use SE030. Check that the line is not stuck low.
B02	Immediately after request	`PP3V3_S5`	3.3V	RE092 or U4801 pin 5	U7800 internal V3P3_SW2 powers CPU VCCPRIM_3P3, VCCDSW_3P3, BATLOW* and other deep-sleep pull-ups. The source notes an approximate 0.5A maximum.	Check U7800 prerequisites and resistance on the S5 3.3V domain.
B03	20ms	`PP1V8_S5`	1.8V	R1850	U7800 BUCK3_SW3 powers CPU VCCPRIM_1P8 and associated control logic.	Check the U7800 output and VCCPRIM_1P8 resistance.
B04	22ms	`PPVPCORE_S5`	About 0.7–1.0V	L7820	U7800 Buck 7 LX0 supplies CPU VCCPRIM_CORE; the source notes approximately 4A maximum. L7820 is the schematic-correct test point.	Check L7820, Buck 7 switching, its enable conditions and core-domain resistance.
B05	24ms	`PP1V_PRIM`	About 1.05V	L7821	U7800 Buck 7 LX1 supplies CPU VCCPRIM_1P05; the source notes approximately 6A maximum.	Check L7821, the shared Buck 7 input/control and VCCPRIM_1P05 loading.
B06	24.5ms	`PCH_PWRBTN_L`	1.8V active-low request	R1463	U7800 SYS_BTN presents the power-button request to U0500. The updated capture places it before PM_RSMRST_L.	Check the SYS_BTN source, R1463 continuity, PCH RTC state and that the signal is not held low.
B07	45ms	`PM_RSMRST_L`	3.3V high after release	R4763	T2 SMC_RSMRST_L releases the Intel RSMRST*/DSW_PWROK deep-sleep domain.	Verify S5 rails, PCH RTC power/clock/reset and the T2 control path.
B08	142ms	`ESPI_RESET_L`	1.8V high after release	J1301 pin 2	The SMC waits for this release before initiating eSPI link training. Pulling this line low prevents the S3 and S0 rail sequence.	Check PM_RSMRST_L, PCH standby conditions, J1301 continuity and any device holding reset low.
B09	145ms	`ESPI_CS_L`	1.8V active-low pulses	R1384 pin 1	Chip-select activity shows that eSPI transactions have begun.	Scope the line. If reset is high but CS is inactive, check T2/PCH power, clocks and continuity.
B10	146ms	`ESPI_CLK60M`	60MHz clock	Accessible eSPI clock point	The 60MHz eSPI clock starts immediately after chip-select activity.	Use a suitable high-bandwidth probe; check clock continuity and T2/PCH eSPI state.
B11	After 146ms	`ESPI_IO<0:3>`	Bidirectional digital activity	eSPI data lanes	Four data lanes perform eSPI link training between the T2/embedded SMC and Intel PCH.	Compare all four lanes. A stuck or missing lane can prevent sleep-state release even when CS and clock are present.
B12	After link training	`SLP_S5_L / SLP_S4_L`	De-asserted through eSPI	Logical eSPI state	The PCH advances out of S5/S4 over eSPI rather than through conventional standalone PM_SLP board checkpoints.	If the link is active but rails do not follow, inspect data integrity, PCH prerequisites and the first missing S3 enable.
B2 - S3 memory, S0 support and Intel IMVP rails
B13	238ms	`PP1V8_S3`	1.8V	R5630 pad; component not stuffed	U7800 BUCK3_SW4 creates PP1V8_S3_MEM for RAM and memory control.	Check U7800 BUCK3_SW4, the R5630 pad and memory-domain resistance.
B14	239ms	`PVDDQ_EN`	Enable high	Memory-regulator enable path	Requests the 1.2V RAM supply after PP1V8_S3 is valid.	If PP1V8_S3 is present but enable is absent, inspect eSPI/PCH sleep-state progression and controlling logic.
B15	240ms	`PP1V2_S3`	1.2V	L8100	The main 1.2V onboard RAM power rail is present.	Check PVDDQ_EN, regulator input/output and RAM-rail resistance.
B16	Same S3 burst	`PP1V_S3`	About 1.3V	C10F0	U7800 BUCK8_SW2 supplies CPU VCCST. The net name contains 1V, but the measured value is about 1.3V.	Check U7800 Buck 8 operation and VCCST loading.
B17	After S3 rails	`SLP_S3_L / SLP_A_L / SLP_LAN_L / SLP_WLAN_L`	De-asserted through eSPI	Logical eSPI state	The PCH releases the remaining S3, auxiliary, LAN and WLAN sleep states and permits S0 support rails.	Confirm eSPI data activity and all S3 rails before checking downstream S0 regulators.
B18	280ms	`PP1V2_S0SW`	1.2V	C10F1	U8207 converts the S3 source into the switched S0 1.2V branch.	Check U8207 input, enable and S0SW resistance.
B19	280.2ms	`PPVCCIO_S0_CPU`	About 0.95V	L8102	U8110 creates the Intel CPU I/O rail.	Check U8110 input and enable, L8102, output capacitors and VCCIO resistance.
B20	After VCCIO stabilises	`PVCCIO_PGOOD`	High	VCCIO PGOOD path	Confirms VCCIO is within regulation and permits later system power-good progression.	If VCCIO is correct, inspect PGOOD output/pull-up. If it is wrong, diagnose U8110 and its load first.
B21	285ms	`ALL_SYS_PWRGD`	1.8V high	R2004	U7800 `SYS_ACTIVE` enables the U7100 Intel IMVP group: CPU core, system-agent and graphics rails.	Verify every preceding S3/S0 support rail and PGOOD. A low ALL_SYS_PWRGD is often a consequence of an earlier failure.
B22	285.5ms	`PPVCCSA_S0_CPU`	About 1.1V	L7270	System-agent rail is produced by the IMVP stage.	Check U7100 command/enable, U7270 driver stage, L7270 and SA-domain loading.
B23	After IMVP rails	`CPU_VR_READY`	1.8V high	R7163	IMVP power system reports that the required CPU voltage regulators are ready.	Scope all CPU rails and power-good outputs; determine which regulator fails before replacing U7100 or CPU.
B24	286ms	`PM_SYSRST_L`	3.3V high after release	R4769	System reset is released immediately after the CPU regulators report ready.	If held low with CPU_VR_READY high, check T2/PCH sequencing, eSPI state and reset-path pull-ups.
B25	291ms	`PM_PCH_PWROK`	3.3V high	R4768	Power-good handoff to the PCH.	Check preceding VR-ready and reset signals plus continuity to U0500.
B26	390ms	`PM_PCH_SYS_PWROK`	3.3V high	R4767	Later system power-good confirms the platform power group is stable.	Capture which input or rail changes immediately before it fails. If it later drops, diagnose the first withdrawn PGOOD rather than treating this signal as the root cause.
B27	725ms	`PLT_RST_L`	1.8V high after release	Accessible same-net device/test point	Intel platform reset is de-asserted; PCIe and platform devices can leave reset.	Verify PCH power-good, clocks and PCH firmware state. A held-low PLT_RST_L is normally downstream evidence of incomplete PCH startup.
B28	726ms	`PPVCC_S0_CPU`	About 0.9V initially; source capture changes to about 0.8V after roughly 1100ms	CPU core inductors	CPU core voltage is active and later adjusted through `CPU_VIDSOUT`/`CPU_VIDSCLK`. A controlled voltage change can be normal.	Check VID clock/data, CPU_VR_READY and whether the rail follows command. A sudden collapse with lost PGOOD requires tracing the first shutdown input.
B29	1745ms	`PPVCCGT_S0_CPU`	Measured pulse to about 0.75V for about 180ms, then 0V	Graphics-rail inductors	Intel integrated-graphics rail is briefly requested in this capture and then disabled. This pulse alone is not proof of a graphics fault.	Correlate the pulse with IMVP command, CPU activity, display request and shutdown signals. Compare duration with a known-good board under the same conditions.
B3 - Internal display and backlight
B30	3125ms	`EDP_PANEL_PWR_EN`	3.3V high	Panel-enable path	U0500/PCH requests internal panel power after the platform has progressed well beyond CPU reset release.	If missing, do not begin at the LCD power switches. Verify PCH startup, display detection policy and preceding resets.
B31	3130ms	`PP3V3_S0SW_LCD`	3.3V	LCD/TCON 3.3V rail	One of the switched TCON/panel logic supplies is present.	Check the panel-power enable, switch/regulator input and display-assembly loading.
B32	3130ms	`PP5V_S0SW_LCD`	5V	LCD/TCON 5V rail	Second switched TCON supply is present.	Check the 5V input source, load switch and panel-side short.
B33	3220ms	`DP_INT_HPD`	3.3V high with a connected, responsive panel	Internal display HPD path	Hot-plug detect tells the Intel display engine that the internal panel/TCON is present.	If both panel rails are correct but HPD is absent, inspect the display connector, cable, panel/TCON and HPD pull-up/path. HPD is expected to be absent with the display disconnected.
B34	3865ms	`EDP_BKLT_EN`	3.3V high	U8400 enable path	The CPU/PCH sends the final backlight enable to U8400 after panel power and HPD.	If image data/panel power are valid but this enable is absent, trace display policy and brightness control. If enable is present, diagnose U8400, backlight power, feedback and the display assembly.

Intel power-state note: the 820-01598 schematic shows T2/SMC coordinating the transition through eSPI. The PCH de-asserts SLP_S5#, SLP_S4#, SLP_S3# and related sleep states over eSPI rather than exposing the traditional standalone PM_SLP signals as the primary board-level sequence checkpoints.

Diagnostic stopping patterns

Observed stopping point	What it proves	Next checks
5V VBUS but no `PPDCIN_G3H`	The charger and cable are providing initial VBUS, but the active CD3217 pass path has not delivered it to the board.	Identify the active port; check its CD3217 power/reset, CC state, internal pass path and downstream PPDCIN resistance.
`PPDCIN_G3H` present but no VDDP or PPBUS	Input has reached U7000 but charger autonomous startup has not completed.	Check U7000 VDDP/VDDA, AUX_DET threshold, switching nodes, current-sense paths and PPBUS short/load.
PPBUS present but no `PP3V3_G3H_RTC`	Charger boost works; the early MVR stage is the next boundary.	Check `CHGR_EN_MVR`, U6903, L6900 and RTC-rail resistance.
CD3217 LDO present but no U2890 SPI	U3200 has power but is not reading the firmware ROM.	Check reset, CS/CLK/MOSI/MISO paths, U2890 supply and ROM integrity. Do not assume firmware corruption until electrical signals are proved.
Calpe rails rise and fall about one second later	U7800 can start, but the T2-PMU handshake or a monitored rail is not staying valid.	Capture 32kHz, 24MHz, SPMI clock/data, cold reset and every awake rail together. Find the first signal withdrawn before the rail collapse.
`PMU_SYS_ALIVE` present but no U4770 SPI	Basic PMU sequencing completed, but T2 ROM access did not begin.	Check `PP1V8_AWAKE`, U4770, T2 clocks, cold reset and SPI continuity.
I2C buses active but VBUS remains 5V	T2 has progressed into communication, but USB-PD policy did not reach a valid 20V contract.	Check CC1/CC2 traffic, charger/cable capability, active CD3217, U2890 SPI data and firmware. Also confirm the observed I2C is addressed communication, not only line noise.
20V and PPBUS correct but no G3S rails	Charger/USB-PD path works; the failure is after the PMU handoff.	Check `PMU_PVDDMAIN_EN`, U7650, P3V3MAIN_PGOOD, PP5V_G3S and secondary U8200/U8220 outputs.
All standby/NAND rails present; board waits	Table A may be complete and T2 has reached power-button monitoring.	Provide a valid `PMU_ONOFF_L` event and observe Table B. Verify top-case/power-button circuitry if the pulse is not generated normally.
`PM_RSMRST_L` missing	S5 rails may be present, but T2/PCH deep-sleep prerequisites are incomplete.	Check PCH RTC 3V, 32kHz, RTC reset, S5 rails and eSPI reset/link conditions.
VCCIO present but `ALL_SYS_PWRGD` missing	The VCCIO regulator works, but one required S3/S0 rail or PGOOD is not accepted.	Check PVDDQ, PP1V2_S3, PP1V_S3, PP1V2_S0SW and PVCCIO_PGOOD before the IMVP stage.
CPU rails pulse, then power-good drops	IMVP received an enable, but the sequence was withdrawn or a rail failed regulation.	Scope ALL_SYS_PWRGD, CPU_VR_READY, PM_SYSRST_L, PM_PCH_PWROK and PM_PCH_SYS_PWROK. Diagnose the earliest falling edge, not the last rail to disappear.
CPU runs but no internal display	Late platform power succeeded; the fault is in the display request, switched rails, HPD, eDP path or backlight stage.	Follow `EDP_PANEL_PWR_EN` -> 3.3V/5V LCD rails -> `DP_INT_HPD` -> `EDP_BKLT_EN`.

How to measure the signals safely

Begin with resistance checks while unpowered. Screen PPBUS, 3.3V RTC, 5V G3S, CPU and NAND rails for an obvious short before repeated power cycling.
Use a common timing trigger. For Table A, trigger on the 5V VBUS edge. For Table B, trigger on the falling edge of PMU_ONOFF_L. Label every capture with its baseline.
Use a 10x high-impedance probe. Crystal and clock nodes are easy to load. Probe at the listed series resistor when possible rather than directly on a fine-pitch IC pin.
Do not call a bus good from its DC voltage. I2C, SPI, SPMI and eSPI require valid transitions and protocol timing. A line sitting at 1.8V only proves it is not presently stuck low.
Interpret active-low names correctly. Signals ending in _L are asserted low and released high. A short low pulse can be the required event rather than a failure.
Capture shutdowns with multiple channels. When a rail pulses, monitor its enable, power-good and the next reset signal together. The first change normally identifies which controller initiated shutdown.

Terminology

ACE2 / UPC

ACE2 refers to the CD3217 USB-C controller generation. UPC means USB-C Port Controller. U3100 and U3200 manage the two port branches.

T2 / embedded SMC

U3900 combines security, bridge and system-management functions. It receives Calpe rails, reads U4770 and coordinates the Intel PCH through eSPI.

Calpe-L PMU

U7800 is Apple PMU 338S00466. It owns much of the early T2, SSD and Intel deep-sleep power sequence.

G3H, G3S, S5, S3 and S0

These suffixes indicate power domains/states. G3H is the earliest always-on hardware supply group; G3S is later standby. S5 and S3 are progressively more active sleep states; S0 is the running state.

SLPS2R

Sleep-to-Running rail group used during T2 wake-up. These rails appear before SYS_ALIVE and T2 ROM access.

SPMI

System Power Management Interface. A dedicated serial link used by T2 and U7800 for power commands and status; it is not ordinary I2C.

eSPI

Enhanced Serial Peripheral Interface between T2/SMC and Intel PCH. On this design, important sleep-state transitions are coordinated over eSPI.

MVR

Early regulator stage enabled by CHGR_EN_MVR. U6903 creates PP3V3_G3H_RTC.

PGOOD / PWRGD

Power-good indication. It means the regulator considers its output valid; a low signal is often a response to an earlier rail problem.

IMVP and VID

Intel Mobile Voltage Positioning controls the CPU core, system-agent and graphics regulators. VID clock/data commands set the requested voltage dynamically.

HPD and TCON

HPD is Hot-Plug Detect from the internal panel. TCON is the display timing controller powered by the switched 3.3V and 5V LCD rails.

PFN and OCARINA

PFN means Power Fail Notification. OCARINA U9000 is the SSD power controller used on the 4-landing option, not the direct Calpe 2-landing branch.

Practical rule: a rail name tells you what the rail feeds, not why it is missing. Always verify the upstream supply, enable, power-good, clock/reset and communication checkpoint immediately before it. On a cycling board, trigger on the first falling PGOOD or reset event rather than the final disappearance of PPBUS or CPU voltage.