ISL9240 Power-On Sequence | A2442 820-02098
Last updated: 16 August 2026
On the 14-inch M1 Pro MacBook Pro A2442 logic board 820-02098, U5200 ISL9240 creates and regulates the main PPBUS_AON supply. It begins with the 5V power passed by CD3217, produces its own VDDA and VDDP bias supplies, operates Q5230 and Q5240 in boost mode, enables PP3V8_AON, and later changes to buck mode after the USB-C input rises to 20V.
This guide also explains the two milliohm current-sensing circuits, how the embedded SMC communicates with U5200, and how to separate an early autonomous charger fault from a later SMC, I2C or USB-PD fault.
Read the preceding CD3217 and ACE-ROM power-on sequence, or return to the complete A2442 M1 Pro power-on sequence.
The measurements and elapsed times are references from a working 820-02098 board. Small variations are normal and depend on the charger, battery state, board state and capture trigger.
Table of Contents
How the ISL9240 fits into the M1 Pro power-on sequence
U5200 does not negotiate USB-C voltage. CD3217 performs USB-PD communication with the charger and passes the accepted adapter voltage into PPDCIN_AON. U5200 then converts that voltage into the approximately 12V system bus required by the logic board.
The important diagnostic boundary is therefore:
- No PPDCIN_AON: remain in the CD3217, ACE-ROM and USB-C power-path stage.
- PPDCIN_AON reaches P_IN but no PPBUS_AON: move into the ISL9240, current-sense and four-switch converter stage.
- Initial 12.3V PPBUS_AON is present but no later 20V: investigate the later PMU, embedded-SMC and CD3217 communication sequence.
ISL9240 sequence overview
- CD3217 passes the initial 5V supply into PPDCIN_AON.
- PPDCIN_AON passes through R5220 and reaches U5200 P_IN.
- CHGR_AUX_DET confirms that the adapter input is valid.
- U5200 produces approximately 5V PPCHGR_VDDA.
- R5275 feeds approximately 5V into PPCHGR_VDDP.
- CELL selects the three-cell operating configuration.
- Q5230, Q5240 and L5230 boost 5V into approximately 12.3V PPBUS_AON.
- EN_MVR asserts P3V8AON_PWR_EN and U5700 creates PP3V8_AON.
- PP1V8_S2 powers the U5200 digital interface and I2C communication starts.
- The embedded SMC coordinates the later 20V USB-PD request through CD3217.
- When P_IN becomes 20V, U5200 changes to buck mode and regulates PPBUS_AON at approximately 12.0V.
Stage 1: PPDCIN_AON reaches P_IN
After CD3217 has loaded its ACE-ROM firmware and enabled its internal power path, the initial USB-C 5V supply appears on PPDCIN_AON. The high-current path passes through R5220 before reaching the input-side half-bridge and the P_IN pin of U5200.
On a working board during this early stage:
- PPDCIN_AON: approximately 5V
- U5200 P_IN: approximately 5V
- CSIP and CSIN: nearly the same DC voltage, separated only by the millivolt drop across R5220
If 5V exists on the CD3217 side but does not reach P_IN, inspect R5220, its pads, the copper path and the current-sense filter components before replacing U5200.
Stage 2: CHGR_AUX_DET validates the adapter
R5215 and R5216 divide PPDCIN_AON into the lower CHGR_AUX_DET voltage used by the AUX_DET input of U5200. With R5215 at 750kΩ and R5216 at 255kΩ:
At 5V input: 5 × 255 ÷ (750 + 255) = approximately 1.27V.
At 20V input: 20 × 255 ÷ (750 + 255) = approximately 5.07V.
Q5216 can pull CHGR_AUX_DET low under control of the ACE circuitry. Therefore, low AUX_DET is not automatically an ISL9240 failure. Inspect R5215, R5216, C5216, Q5216 and CHGR_AUX_DET_3V3.
Stage 3: PPCHGR_VDDA, PPCHGR_VDDP and CELL
Once P_IN and AUX_DET are valid, the internal linear regulator in U5200 creates approximately 5V PPCHGR_VDDA. This is the analog and internal control supply.
PPCHGR_VDDA feeds PPCHGR_VDDP through R5275, a 4.7Ω resistor. PPCHGR_VDDP supplies the MOSFET gate-driver circuits. C5275 and C5277 provide local filtering and energy storage.
- PPCHGR_VDDA: approximately 5.0V to 5.1V
- PPCHGR_VDDP: approximately 5.0V to 5.1V
- CELL high: three-cell configuration used by the A2442
- CELL low: two-cell configuration
An open or corroded R5275 can leave one supply present while the other is missing. See our A2442 R5275 water-damage case study for a real repair example.
Stage 4: How Q5230, Q5240 and L5230 work
U5200 controls a four-switch synchronous buck-boost converter. Q5230 contains the input-side Q1 and Q2 MOSFETs. Q5240 contains the output-side Q3 and Q4 MOSFETs. L5230, a 2.7µH inductor, connects CHGR_PHASE1 to CHGR_PHASE2.
| Mode | Q1 and Q2 in Q5230 | Q3 and Q4 in Q5240 | Result |
|---|---|---|---|
| Boost | Q1 remains on; Q2 remains off | Q3 and Q4 switch alternately | Raises 5V to approximately 12.3V |
| Buck | Q1 and Q2 switch alternately | Q3 remains off; Q4 remains on | Reduces 20V to approximately 12.0V |
| Buck-boost transition | Q1 and Q2 are actively controlled | Q3 and Q4 are actively controlled | Maintains the system bus while input voltage crosses the output range |
BOOT1 and BOOT2 are bootstrap supplies for the high-side MOSFET gate drivers. U5200 also inserts dead time so that the high-side and low-side MOSFET in one half-bridge are not fully on simultaneously.
Initial 5V boost operation
With a 5V input and a required system bus near 12.3V, Q1 supplies the inductor path while Q3 and Q4 switch alternately. During one part of the cycle the inductor stores magnetic energy; during the other part it transfers that energy into PPVBAT_AON_CHGR_REG. F5200 and F5201 connect this regulated output to PPBUS_AON.
The reference board reaches approximately 12.3V PPBUS_AON at about 800ms. This early boost is autonomous and does not require the embedded SMC to have started I2C communication.
How the R5220 and R5260 current-sensing circuits work
The two sense resistors appear almost like short circuits on an ordinary resistance meter because their values are measured in milliohms. They are deliberately placed in the high-current paths so U5200 can calculate current from a very small differential voltage.
The relationship is:
Current = measured voltage difference ÷ sense resistance
R5220: adapter and input-current sensing
R5220 is the 0.010Ω input current-sense resistor for the three-cell A2442 configuration. It is positioned between PPDCIN_AON and the converter input. Current flowing into the board produces a small voltage drop:
- 1A: 1 × 0.010Ω = 10mV
- 3A: 3 × 0.010Ω = 30mV
- 5A: 5 × 0.010Ω = 50mV
CSIP senses the source-positive side and CSIN senses the converter side. U5200 uses their difference to enforce the adapter current limit and to calculate the adapter-current monitor output, AMON.
R5221 and R5222 are the 1Ω series filter resistors. C5221 and C5222 filter each sense input to ground, while C5220 provides differential filtering across the filtered CSIP and CSIN pair. These components prevent switching spikes from being interpreted as real input current.
Fault interpretation: an open R5220 removes the main input path and P_IN will be missing. An open Kelvin trace or filter resistor can allow power to pass while causing incorrect current measurement, protection triggering or unstable conversion.
R5260: battery charge and discharge-current sensing
R5260 is the 0.005Ω battery-side current-sense resistor used by the three-cell configuration. It sits between the regulated charger/system node and the battery MOSFET path controlled through BGATE and Q5265.
- 1A: 1 × 0.005Ω = 5mV
- 5A: 5 × 0.005Ω = 25mV
- 10A: 10 × 0.005Ω = 50mV
CSOP and CSON measure the differential voltage across R5260. The polarity identifies whether current is charging the battery or flowing from the battery back toward the system. U5200 uses this information for charge-current regulation, battery-current protection and the BMON battery-current monitor output.
R5261, R5262, C5260, C5261 and C5262 form the battery-sense differential filter. An open R5260 can disconnect battery current while adapter-only PPBUS_AON may still be present. A fault in the Kelvin-sense or filter path can instead produce incorrect current reporting or charger shutdown.
Why a multimeter voltage-to-ground reading is not enough
The useful current signal is the difference between the two sense inputs, often only 5mV to 50mV. Both sides may measure almost the same voltage to ground. For accurate diagnosis, compare the two Kelvin-sense points directly with suitable differential measurement equipment and observe correct probe polarity.
Stage 5: EN_MVR enables PP3V8_AON
After PPBUS_AON is stable, U5200 asserts EN_MVR. On 820-02098 the signal is named P3V8AON_PWR_EN and the schematic identifies it as an approximately 5V enable.
P3V8AON_PWR_EN enables U5700, which converts PPBUS_AON into approximately 3.8V PP3V8_AON.
- PPBUS_AON correct but P3V8AON_PWR_EN missing: U5200 has not completed the early charger stage or has detected a fault.
- P3V8AON_PWR_EN present but PP3V8_AON missing: move the diagnosis to U5700, its driver supplies, switching stages and PP3V8_AON load.
How the embedded SMC communicates with U5200
The embedded SMC does not have to communicate with U5200 for the first 5V-to-12.3V boost. U5200 can start autonomously from P_IN, AUX_DET, its bias rails and the CELL hardware configuration. This is essential because the embedded SMC cannot run until the earlier always-on power rails exist.
The 1.8V I2C interface
After the MPMU creates PP1V8_S2, this rail powers the VDDIO1P8 pin of U5200. The digital interface can then communicate through:
- I2C_SMC_PWR_1V8_SDA: bidirectional 1.8V serial data
- I2C_SMC_PWR_1V8_SCL: 1.8V serial clock
Through this I2C connection, the embedded SMC can read charger state and faults and program operating limits such as allowable adapter current, system voltage and battery charge current. Apple-specific register programming is proprietary, but the observable electrical interface is the 1.8V SDA/SCL bus.
Interrupt, reset and status signals
- CHGR_INT_1V8_L: active-low interrupt from U5200 requesting attention from the management logic
- CHGR_RST_IN: reset input used to reset or hold U5200
- CHGR_AUX_OK: open-drain indication that the qualified adapter condition is valid
- AMON: analog representation of adapter/input current measured through R5220
- BMON: analog representation of battery current measured through R5260
AMON and BMON are analog monitor outputs, not I2C packets. They are routed into the board’s monitoring circuitry so the power-management system can observe current independently of the digital status registers.
Reference communication order
| Approximate time | Signal or event | Meaning |
|---|---|---|
| 800ms | PPBUS_AON ≈12.3V | Autonomous boost has completed |
| 1000ms | PP3V8_AON ≈3.8V | U5700 and early PMU supply are running |
| 3150ms | PP1V8_S2 | U5200 VDDIO1P8 and the 1.8V I2C domain can operate |
| 4210ms | I2C_SMC_PWR activity | Embedded SMC communicates with U5200 |
| 4230ms | I2C_SMC_UPC activity | Embedded SMC communicates with CD3217 on a separate bus |
| 4400ms | PPDCIN_AON rises to ≈20V | CD3217 and the charger have completed the higher-voltage contract |
| 5200ms | PPBUS_AON ≈12.0V | U5200 has changed to buck-mode regulation |
The separate buses matter diagnostically. The embedded SMC communicates with U5200 on I2C_SMC_PWR, but it coordinates USB-C power negotiation with CD3217 on I2C_SMC_UPC. U5200 does not transmit USB-PD packets on CC1 or CC2.
Stage 6: 20V USB-PD input and buck mode
After the embedded SMC and CD3217 communication becomes active, CD3217 negotiates approximately 20V from the USB-C charger. PPDCIN_AON and U5200 P_IN then rise from approximately 5V to approximately 20V.
Because the input is now higher than the required PPBUS_AON voltage, U5200 changes to buck mode:
- Q1 and Q2 in Q5230 switch alternately.
- Q3 remains off.
- Q4 remains on.
- L5230 and the output capacitors smooth the PWM energy into approximately 12.0V PPBUS_AON.
The change from approximately 12.3V in initial boost mode to approximately 12.0V in later buck mode is normal. It should not be mistaken for a collapsing PPBUS rail.
Reference measurements on a working 820-02098
| Checkpoint | Initial stage | Later stage | What it confirms |
|---|---|---|---|
| PPDCIN_AON | ≈5V | ≈20V | CD3217 power path and later USB-PD contract |
| U5200 P_IN | ≈5V | ≈20V | Adapter input reaches U5200 through R5220 |
| CHGR_AUX_DET | ≈1.27V | ≈5.07V | Adapter-detection divider is operating |
| PPCHGR_VDDA | ≈5.0–5.1V | ≈5.0–5.1V | Internal analog bias is present |
| PPCHGR_VDDP | ≈5.0–5.1V | ≈5.0–5.1V | R5275 and gate-driver supply are intact |
| PPBUS_AON | ≈12.3V | ≈12.0V | Boost mode followed by buck mode |
| P3V8AON_PWR_EN | ≈5V when asserted | ≈5V | U5200 has enabled U5700 |
| PP3V8_AON | ≈3.8V | ≈3.8V | U5700 and following PMU stage can operate |
Recommended diagnostic order
- Confirm PPDCIN_AON reaches 5V.
- Confirm P_IN receives 5V after R5220.
- Measure CHGR_AUX_DET for approximately 1.27V.
- Measure PPCHGR_VDDA and PPCHGR_VDDP for approximately 5V.
- Compare both sides of R5275.
- Check PPBUS_AON resistance to ground before investigating switching.
- Confirm the two sense paths and their 1Ω filter resistors are continuous.
- Use an oscilloscope to inspect CHGR_PHASE1, CHGR_PHASE2 and the gate-drive stage.
- Confirm PPBUS_AON reaches approximately 12.3V.
- Confirm P3V8AON_PWR_EN rises to approximately 5V and PP3V8_AON reaches 3.8V.
- After PP1V8_S2 appears, inspect I2C_SMC_PWR_1V8_SDA and SCL.
- Confirm the later 20V USB-PD transition and approximately 12.0V buck-mode PPBUS_AON.
Common ISL9240 fault patterns
| Measurement pattern | Likely fault area |
|---|---|
| No PPDCIN_AON | CD3217, ACE-ROM, USB-C input or CD3217 internal power path |
| 5V before R5220 but no P_IN | R5220, pads or high-current trace |
| P_IN correct but AUX_DET low | R5215, R5216, C5216, Q5216 or ACE control |
| P_IN and AUX_DET correct but VDDA missing | VDDA short, damaged U5200 or internal LDO fault |
| VDDA present but VDDP missing | R5275 open, VDDP short or damaged connection |
| Bias rails correct but no PPBUS_AON | U5200, Q5230, Q5240, L5230, bootstrap network, current-sense path or PPBUS short |
| 12.3V PPBUS present but no EN_MVR | U5200 has not qualified the output or has detected a fault |
| EN_MVR present but PP3V8_AON missing | U5700 stage or a short on PP3V8_AON |
| 12.3V present but no I2C_SMC_PWR | Missing PP1V8_S2, embedded-SMC startup or I2C fault |
| I2C_SMC_PWR active but no 20V | Later SMC-to-CD3217 bus, ACE firmware, CD3217 or charger contract |
| 20V input present but PPBUS unstable | Buck-mode Q5230/Q5240 drive, L5230, sensing circuit or excessive output load |
Terminology used in this guide
| Term | Full name or meaning | Function |
|---|---|---|
| ISL9240 | Renesas/Intersil charger-controller part number | Controls system-bus regulation, charging and the four-switch converter |
| SPI | Serial Peripheral Interface | Used by CD3217 to read its ACE-ROM in the preceding stage |
| I2C | Inter-Integrated Circuit | Two-wire serial bus used by the embedded SMC, U5200 and CD3217 |
| SMBus | System Management Bus | I2C-derived protocol commonly used for batteries and charger management |
| SMC | System Management Controller | Embedded management logic responsible for power, charging and hardware control |
| USB-PD | Universal Serial Bus Power Delivery | Protocol used by CD3217 and the USB-C charger to negotiate voltage and current |
| P_IN | Power Input | Adapter-derived power input for U5200 |
| VDDA | Analog Supply Voltage | Approximately 5V internal analog and control supply |
| VDDP | Gate-Driver Power Supply | Approximately 5V supply for the Q1–Q4 gate drivers |
| CELL | Battery Cell-Count Select | Selects the two-cell or three-cell configuration |
| MOSFET | Metal-Oxide-Semiconductor Field-Effect Transistor | High-speed electronic power switch |
| NFET | N-channel Field-Effect Transistor | MOSFET type used in Q5230 and Q5240 |
| PWM | Pulse-Width Modulation | Controls MOSFET on-time to regulate voltage and current |
| CSIP / CSIN | Current-Sense Input Positive / Negative | Measure adapter current across R5220 |
| CSOP / CSON | Battery-Side Current-Sense Positive / Negative | Measure charge and discharge current across R5260 |
| AMON | Adapter Current Monitor | Analog output representing input current |
| BMON | Battery Current Monitor | Analog output representing battery current |
| LX1 / LX2 | Inductor Switching Nodes 1 / 2 | Fast-switching nodes on either side of L5230 |
| BOOT1 / BOOT2 | Bootstrap Gate-Driver Supplies | Drive the high-side N-channel MOSFET gates |
| EN_MVR | Enable Main Voltage Regulator | Enables U5700 and the PP3V8_AON stage |
| IRQ | Interrupt Request | Active-low notification that U5200 requires management attention |
| AON | Always On | Rail required during the earliest power states |
| Boost | Step-Up Conversion | Raises the initial 5V input to approximately 12.3V |
| Buck | Step-Down Conversion | Reduces the later 20V input to approximately 12.0V |
| Buck-boost | Step-Down and Step-Up Conversion | Maintains the system bus across changing input voltages |
| Kelvin sense | Separate low-current voltage-sense connection | Measures the millivolt drop across a high-current resistor accurately |
| Dead time | Delay between complementary MOSFET switching | Prevents both MOSFETs in a half-bridge from conducting simultaneously |
Frequently asked questions
Does U5200 negotiate 20V with the USB-C charger?
No. CD3217 performs USB-PD communication. U5200 converts and regulates the voltage that CD3217 passes into PPDCIN_AON.
Why is PPBUS_AON available while the charger is still at 5V?
U5200 operates Q5230 and Q5240 in boost mode to create approximately 12.3V. This allows the PMU and embedded SMC to start before the higher-voltage USB-PD contract.
Does the first 12.3V boost require I2C communication?
No. The initial boost is autonomous. The U5200 I2C interface becomes available later when PP1V8_S2 powers VDDIO1P8.
Why does PPBUS_AON change from 12.3V to approximately 12.0V?
The first value is produced while U5200 boosts from a 5V input. After the input reaches 20V, U5200 changes to buck mode and regulates the system bus near 12.0V.
Can I calculate current from AMON or BMON alone?
The monitor outputs are useful, but direct current calculation requires the monitor scaling used by the board design. The most fundamental measurement is the differential voltage across the known R5220 or R5260 resistance.
Can I diagnose Q5230 and Q5240 with only a multimeter?
A multimeter can identify a shorted device or missing static supply. Confirming gate timing and switching operation requires an oscilloscope.
Measurement and safety notes
Use DC measurements for P_IN, AUX_DET, VDDA, VDDP, PPBUS_AON and EN_MVR. Use an oscilloscope for GATE_Q1 to GATE_Q4, CHGR_PHASE1, CHGR_PHASE2 and I2C.
Never connect a grounded oscilloscope clip directly to a floating switching node. An incorrect ground connection can short the charger circuit and damage U5200, Q5230 or Q5240.
Disconnect all power before resistance or diode-mode testing. The sense resistors are supposed to measure close to zero ohms; confirm them using continuity, known-good comparison and four-wire measurement when precise resistance is required.
Continue with the full M1 Pro sequence
Once PPBUS_AON and PP3V8_AON are stable, the sequence continues into the MPMU, SPMU and early SoC always-on rails. Return to the complete A2442 820-02098 M1 Pro power-on sequence to continue the diagnosis.
