Embedded SMC and SoC ROM Startup Sequence – A2442 820-02098
Last updated: 17 August 2026
Stage 4 of the A2442 M1 Pro power-on sequence begins after the Viper and MONACO regulators have created the required SoC awake rails. MPMU U8100 then releases the M1 Pro from reset, confirms that the PMU active state is ready, and permits the embedded System Management Controller to begin firmware-controlled board management.
This guide follows a measured working 14-inch MacBook Pro A2442 logic board 820-02098. It explains checkpoints 35–44: PMU_RESET_L, PMU_SYS_ALIVE, PMU_ACTIVE_READY, the 24MHz SoC clock, U2010 SoC-ROM access, IPD_PWR_EN_PMU, SPMI traffic and the three I²C communication paths used for power, USB-C and NAND control.
Read the preceding Viper, MONACO and SoC awake-rail sequence, or return to the complete A2442 M1 Pro power-on sequence.
The measured times are working-board references, not universal pass-or-fail specifications. Charger, battery, temperature, logic-board configuration and capture trigger can change the observed timing.
Table of Contents
Where Stage 4 begins and ends
Stage 4 begins only after the Stage 3 outputs are stable. The immediate prerequisites are PP1V8_S1_CLVR_VDDH and the CPU, GPU, ANE, SRAM and fabric awake rails created by the Viper and MONACO stage.
Stage 4 then performs four jobs:
- MPMU U8100 releases the SoC and reports its active state.
- The M1 Pro receives its 24MHz reference clock and attempts to read U2010 through SPI.
- The embedded SMC begins later enable and PMU-management activity.
- The embedded SMC communicates with the charger, USB-C controllers and NAND PMIC.
Stage 4 ends after I2C_NAND_PMIC_SDA_1V8 activity is observed at about 4320ms. The first NAND supply, PP1V2_NAND0, appears at about 4326ms and therefore belongs to Stage 5.
Stage 4 sequence overview
Stage 4 prerequisites
Do not begin at U2010 merely because the Mac does not boot. A missing earlier rail can prevent every Stage 4 signal while leaving the ROM circuit completely healthy.
| Prerequisite | Expected condition | Why it matters |
|---|---|---|
| PP3V8_AON and PMU always-on rails | Stable | Keep U8100 operating throughout the hand-off |
| PP1V8_S1_CLVR_VDDH | Approximately 1.8V | Supplies the MONACO regulator stage |
| CPU, GPU, ANE and fabric awake rails | Appear and remain stable | Power the SoC domains that must execute the next startup phase |
| PP1V8_AWAKE | Approximately 1.8V | Supplies U2010 and its SPI translation circuitry |
| Stage 4 output resistance | No abnormal short on awake or ROM supplies | Prevents an immediate reset or power collapse |
MPMU hand-off to the M1 Pro
U8100 MPMU remains the power-sequence owner at the start of this stage. Three signals appear close together, but they should not be treated as interchangeable.
PMU_RESET_L
PMU_RESET_L rises to approximately 1.2V at about 3200ms and can be measured at R8321. The _L suffix means active low: low asserts reset and high releases it. The reference capture records that the embedded SMC does not begin the SoC-ROM read if this signal is absent.
If PMU_RESET_L remains low, first confirm the complete Stage 3 rail set and U8100 supplies. Replacing U2010 cannot repair a SoC that is still held in reset.
PMU_SYS_ALIVE
PMU_SYS_ALIVE rises to approximately 1.8V at about 3200ms and is accessible at R8319. It announces that the system power state is alive and permits NAND, SSD and other later enable paths.
The measured notes distinguish this signal from the ROM prerequisite: U2010 may still be read when PMU_SYS_ALIVE is missing, but NAND and related outputs will not progress normally. This makes PMU_SYS_ALIVE a useful separator between “the SoC can start reading” and “the board can continue enabling later devices.”
PMU_ACTIVE_READY
PMU_ACTIVE_READY rises to approximately 1.2V at about 3200.063ms and can be measured at R8320. It tells the M1 Pro that U8100 has reached the PMU active state.
If PMU_RESET_L is high but PMU_ACTIVE_READY is missing, the M1 Pro may be released electrically without receiving a valid PMU-ready condition. Confirm U8100 state, clock, supplies and the earlier awake rails before investigating U2010.
What “embedded SMC” means on Apple silicon
On older Intel Mac logic boards, the SMC is a separate controller. On this M1 Pro board the system-management function is embedded within the Apple SoC. The schematic therefore shows SMC-named I²C buses originating from the M1 Pro rather than from a separate SMC IC.
The embedded SMC performs board-management tasks such as communicating with U5200 ISL9240, the CD3217 USB-C port controllers and the NAND PMIC. This does not mean that every observed bus transaction comes from one software routine; it means that the management controller and its interfaces are part of the SoC package.
The 24MHz SoC reference clock
Y0600 supplies the SoC 24MHz reference through SOC_XTAL24M_IN. The measured reference records a DC average near 0.572V or 0.596V at the crystal area, but that value alone does not prove that a 24MHz waveform exists.
A multimeter averages a rapidly changing signal. Use a suitable high-impedance, low-capacitance oscilloscope probe and compare with a known-good board. Access may require removal of the SoC back cover or shield. Loading the crystal node with the wrong probe can stop or distort oscillation.
If the clock is absent, inspect Y0600, its load network, the related SoC power domains and physical damage around the crystal before blaming U2010.
U2010 SoC ROM startup through SPI
U2010 is the external 1.8V, 64Mbit SPI NOR device used by the SoC startup path. It is supplied by PP1V8_AWAKE. The schematic shows level-shifting and support components on the chip-select, clock and data paths between U2010 and the M1 Pro.
At about 3376ms, SPI_SOCROM_1V8_CS_L falls from approximately 1.8V to 0V. R2011 is the practical checkpoint. This falling edge is the first strong sign that the M1 Pro is attempting to access the external SoC ROM.
What each SPI signal does
| Signal | Full name | Function | What to expect |
|---|---|---|---|
| CS_L | Chip Select, active low | Selects U2010 for a transaction | Normally high, then pulses low during access |
| CLK | Serial Clock | Times each transferred bit | Clock bursts while CS_L is low |
| MOSI | Master Out, Slave In | Carries commands and addresses from the SoC to U2010 | Data transitions during the transaction |
| MISO | Master In, Slave Out | Returns ROM data from U2010 to the SoC | Data transitions after the read command |
Why CS_L alone is not enough
A falling CS_L proves that the SoC attempted a transaction. It does not prove that CLK is correct, that MOSI contains a valid command, that U2010 returns correct MISO data, or that the firmware contents are valid.
For a suspected ROM fault, capture CS_L, CLK, MOSI and MISO together. Also verify PP1V8_AWAKE, the series resistors, level translators and continuity to both U2010 and the SoC. A correct DC voltage on a data line is not a substitute for waveform inspection.
SoC ROM is not the CD3217 ACE-ROM
| ROM | Controller that reads it | When it is used | Purpose in this sequence |
|---|---|---|---|
| ACE-ROM | CD3217 USB-C port controller | Stage 1, after dead-battery power-up | Loads USB-C / PD controller firmware and configuration |
| U2010 SoC ROM | M1 Pro SoC | Stage 4, after PMU reset release | Supports SoC startup and embedded-SMC initialization |
A board can pass the CD3217 ACE-ROM stage and still fail at U2010. Conversely, an early ACE-ROM failure can prevent the board from reaching the PMU and SoC-ROM stages at all.
IPD_PWR_EN_PMU and later enable control
IPD_PWR_EN_PMU rises to approximately 1.8V at about 3750ms. The measured checkpoint is PPU8B1. It shows that U8100 has moved beyond the initial SoC-ROM access and has started a later enable path.
The schematic does not publish an authoritative expansion for the Apple net prefix IPD, so this guide retains the original signal name rather than inventing one. Use it as a sequence checkpoint: if the SoC-ROM transaction occurs but IPD_PWR_EN_PMU never appears, diagnose the hand-off between ROM startup, embedded-SMC execution and U8100 control.
SPMI communication with U8100
SPMI_NUB_MPMU_DATA shows a data waveform at about 3760ms, with R2105 used as a practical measurement point. SPMI means System Power Management Interface. It is a digital control bus used between the M1 Pro management logic and U8100.
The reference notes that this particular NUB data checkpoint does not determine boot by itself. Treat it as supporting evidence of PMU communication, not as a stand-alone pass/fail signal. Use a scope or logic analyser; a multimeter can show an average voltage while completely missing malformed or absent packets.
Embedded-SMC I²C communication order
After the initial SoC-ROM and PMU communication, the embedded SMC begins three practical I²C transactions. These buses use separate nets and control different devices.
I2C_SMC_PWR_1V8_SDA to U5200 ISL9240
At about 4210ms, I2C_SMC_PWR_1V8_SDA shows I²C activity at RD117. This is the embedded-SMC power-management bus to U5200 ISL9240.
Earlier in Stage 1, U5200 can create approximately 12.3V PPBUS_AON in boost mode without this later software conversation. The Stage 4 I²C transaction permits the embedded SMC to read status and program the charger for the running system. If this bus is inactive, PPBUS_AON may fail to make its later controlled transition even though the initial boost rail exists.
I2C_SMC_UPC_SDA to the CD3217 controllers
At about 4230ms, I2C_SMC_UPC_SDA shows I²C activity at RD190. UPC is the Apple net prefix used for the USB-C port-controller bus. The embedded SMC uses this path to communicate with the CD3217 controllers.
If the bus is missing, the later USB-C negotiation and 20V PPDCIN_AON transition may not occur. If SMC-side activity reaches RD190 but one controller does not respond, investigate that controller, its ACE-ROM, supplies, reset and local bus path.
I2C_NAND_PMIC_SDA_1V8 to UN400
At about 4320ms, I2C_NAND_PMIC_SDA_1V8 shows communication with UN400, the NAND power-management IC. This is the final Stage 4 checkpoint.
Bus activity proves that the embedded SMC has reached the NAND-PMIC command stage. It does not prove that UN400 accepted the command or created its outputs. If this waveform is present but PP1V2_NAND0 is missing, Stage 4 has passed and diagnosis should continue with UN400 supplies, enables, NAND-rail resistance and the Stage 5 sequence.
Bus ownership and expected test method
| Signal or bus | Owner / destination | Preferred tool | Diagnostic meaning |
|---|---|---|---|
| PMU_RESET_L | U8100 to M1 Pro | Multimeter or oscilloscope | SoC reset is released |
| SOC_XTAL24M_IN | Y0600 to M1 Pro | Low-capacitance oscilloscope probe | 24MHz reference clock is present |
| SPI_SOCROM_1V8_CS_L / CLK / MOSI / MISO | M1 Pro and U2010 | Oscilloscope or logic analyser | SoC attempts and completes a ROM transaction |
| SPMI_NUB_MPMU_DATA | M1 Pro and U8100 | Oscilloscope or logic analyser | Power-management control traffic |
| I2C_SMC_PWR_1V8_SDA | Embedded SMC and U5200 | Oscilloscope or logic analyser | Charger configuration and status communication |
| I2C_SMC_UPC_SDA | Embedded SMC and CD3217 | Oscilloscope or logic analyser | USB-C controller communication |
| I2C_NAND_PMIC_SDA_1V8 | Embedded SMC and UN400 | Oscilloscope or logic analyser | NAND-PMIC command stage has begun |
Complete measured Stage 4 order
| Step | Time | Signal or rail | Expected | Test point | Meaning | If missing |
|---|---|---|---|---|---|---|
| 35 | 3200ms | PMU_RESET_L | ≈1.2V high | R8321 | U8100 releases embedded SMC / SoC reset | SoC does not begin the ROM read |
| 36 | 3200ms | PMU_SYS_ALIVE | ≈1.8V high | R8319 | Allows SSD, NAND and other later paths | Later outputs missing; SoC ROM may still be read |
| 37 | 3200.063ms | PMU_ACTIVE_READY | ≈1.2V high | R8320 | MPMU active state is ready | SoC does not begin the ROM read |
| 38 | Before ROM access | SOC_XTAL24M_IN | 24MHz waveform; DC average ≈0.572V / 0.596V | CPU / SMC crystal area | SoC reference clock | Clock path or SoC-domain fault |
| 39 | 3376ms | SPI_SOCROM_1V8_CS_L | Drops 1.8V → 0V | R2011 | M1 Pro selects U2010 | SoC ROM is not being accessed |
| 40 | 3750ms | IPD_PWR_EN_PMU | ≈1.8V | PPU8B1 | Later PMU-controlled enable starts | Sequence may stop before bus hand-off |
| 41 | 3760ms | SPMI_NUB_MPMU_DATA | Data waveform | R2105 | M1 Pro communicates with U8100 | SPMI fault; reference notes this checkpoint alone does not determine boot |
| 42 | 4210ms | I2C_SMC_PWR_1V8_SDA | I²C waveform | RD117 | Embedded SMC communicates with U5200 | Later PPBUS_AON control may be missing |
| 43 | 4230ms | I2C_SMC_UPC_SDA | I²C waveform | RD190 | Embedded SMC communicates with CD3217 | No later 20V PPDCIN_AON; inspect USB-C controller and ACE-ROM path |
| 44 | 4320ms | I2C_NAND_PMIC_SDA_1V8 | I²C waveform | NAND-PMIC bus | Embedded SMC communicates with UN400 | No NAND rails; continue at Stage 5 |
Recommended diagnostic order
- Confirm every Stage 3 rail remains stable long enough for Stage 4.
- Measure PMU_RESET_L at R8321, PMU_SYS_ALIVE at R8319 and PMU_ACTIVE_READY at R8320.
- Confirm PP1V8_AWAKE at U2010 and the SPI support circuit.
- Verify the 24MHz crystal waveform with a suitable probe.
- Capture SPI_SOCROM_1V8_CS_L at R2011.
- If CS_L falls, capture CLK, MOSI and MISO during the same transaction.
- Check IPD_PWR_EN_PMU at PPU8B1.
- Observe SPMI_NUB_MPMU_DATA at R2105 as supporting evidence.
- Capture I2C_SMC_PWR_1V8_SDA at RD117.
- Capture I2C_SMC_UPC_SDA at RD190 and confirm controller response.
- Capture I2C_NAND_PMIC_SDA_1V8.
- Stop at the last confirmed checkpoint and diagnose its immediate owner rather than jumping to the SoC.
Common Stage 4 fault patterns
| What you observe | Most useful interpretation |
|---|---|
| PMU_RESET_L and PMU_ACTIVE_READY both missing | Stage 3 rail, U8100 supply, PMU state or earlier power-sequence fault |
| PMU_RESET_L high but no 24MHz clock | Crystal circuit, SoC clock domain or probe-loading issue |
| Clock and resets correct but CS_L never falls | SoC has not attempted U2010 access; check PP1V8_AWAKE, SPI path and SoC startup prerequisites |
| CS_L and CLK active but MISO remains inactive | U2010 supply, ROM device, data path or level-translator fault |
| All four SPI signals active but startup stops | Possible invalid ROM data, later firmware hand-off failure or another SoC prerequisite; compare waveform and contents with known good |
| SoC ROM access present but IPD_PWR_EN_PMU absent | Failure after ROM attempt and before later PMU enable |
| I2C_SMC_PWR active but I2C_SMC_UPC absent | Embedded-SMC sequence stops before USB-C communication |
| I2C_SMC_UPC active but no 20V transition | CD3217 response, ACE-ROM, USB-PD or port power-path fault |
| I2C_NAND_PMIC active but PP1V2_NAND0 missing | Stage 4 passed; diagnose UN400 and Stage 5 |
Terminology used in this guide
| Term | Full name or meaning | Function in Stage 4 |
|---|---|---|
| SMC | System Management Controller | Board-management function embedded in the M1 Pro SoC |
| SoC | System on a Chip | M1 Pro package containing CPU, GPU, controllers and embedded management logic |
| ROM | Read-Only Memory | Non-volatile startup firmware or configuration storage |
| SPI | Serial Peripheral Interface | Four-signal serial bus used to read U2010 |
| CS_L | Chip Select, active low | Selects the SPI ROM while low |
| CLK | Clock | Times serial data transfer |
| MOSI | Master Out, Slave In | Commands and addresses from M1 Pro to U2010 |
| MISO | Master In, Slave Out | ROM data returned from U2010 to M1 Pro |
| NOR | Non-volatile flash-memory architecture | Memory technology used by U2010 |
| MPMU | Main Power Management Unit | U8100 controls reset, status and later enable signals |
| SPMI | System Power Management Interface | Serial management bus between the SoC and U8100 |
| I²C | Inter-Integrated Circuit | Two-wire serial bus using SDA and SCL |
| SDA | Serial Data | Bidirectional I²C data line |
| SCL | Serial Clock | I²C clock line |
| UPC | USB-C Port Controller in Apple net naming | CD3217 communication bus |
| PMIC | Power Management Integrated Circuit | UN400 creates and controls NAND supply rails |
| IPD | Apple net prefix; expansion not defined in this schematic | Names a later PMU-controlled enable path |
| NUB | Apple management-bus label; expansion not defined in this schematic | Identifies the recorded SPMI data path |
| _L suffix | Active-low signal | The named function is asserted while the signal is low |
Frequently asked questions
Is the Apple-silicon SMC a separate chip?
No. On this A2442 M1 Pro board the system-management function is embedded in the SoC. The SMC-named buses therefore connect from the M1 Pro to the controlled devices.
Does a low pulse on SPI_SOCROM_1V8_CS_L prove that U2010 is good?
No. It proves only that the SoC attempted to select U2010. Check CLK, MOSI and MISO to confirm a complete transaction, and consider ROM contents only after the electrical paths are proven.
Can PMU_SYS_ALIVE be missing while the SoC ROM is still read?
Yes, according to the measured reference notes. PMU_SYS_ALIVE mainly permits later SSD, NAND and other output paths, while PMU_RESET_L and PMU_ACTIVE_READY are the direct ROM-start prerequisites in this capture.
Can a multimeter test I²C, SPI or SPMI?
It can reveal a stuck-low line or missing pull-up, but it cannot prove valid digital communication. Use an oscilloscope or logic analyser for timing and data activity.
Does NAND-PMIC I²C activity mean the NAND power rails are good?
No. It means the command stage was reached. The NAND PMIC must still accept the command and create PP1V2_NAND0, PP0V9_NAND0 and the later rails in Stage 5.
Should U2010 be replaced whenever a board stops at Stage 4?
No. First prove reset release, PMU-ready status, PP1V8_AWAKE, the 24MHz clock and all four SPI signals. A missing prerequisite can make a good U2010 appear inactive.
Measurement and safety notes
Use DC voltage measurement for PMU_RESET_L, PMU_SYS_ALIVE, PMU_ACTIVE_READY, PP1V8_AWAKE and IPD_PWR_EN_PMU. Use an oscilloscope or logic analyser for the crystal, SPI, SPMI and I²C signals.
Disconnect all power before resistance, continuity or diode-mode testing. Use a fine probe and board support to prevent slipping between small 1.8V logic nodes and adjacent rails. Avoid long ground leads when viewing high-speed edges.
Do not inject voltage into a crystal, SPI, SPMI or I²C line. Do not remove or rewrite U2010 until its supply, bus path and original contents have been backed up and the earlier prerequisites are proven.
Continue to Stage 5
Once I2C_NAND_PMIC_SDA_1V8 activity is present, the embedded SMC has reached the NAND power-management hand-off. The next checkpoint is PP1V2_NAND0 at approximately 4326ms, followed by PP0V9_NAND0, P2V5_NAND0_EN, PP2V5_NAND0 and NAND_RESET_L. Return to the complete A2442 820-02098 M1 Pro power-on sequence and continue with Stage 5.
