Intel MacBook PM_SLP_S4_L Missing: Power-On Sequence and Diagnosis
PM_SLP_S4_L is one of the most useful checkpoints on older Intel Mac logic boards. If PP3V3_S5 is present but PP5V_S3, PP3V3_S3 or the memory rail never appears, this signal helps identify where the power-on sequence stopped. However, a 0 V multimeter reading does not automatically prove that the CPU or PCH has failed.
The correct diagnosis depends on whether PM_SLP_S4_L remains continuously low, rises briefly before collapsing, or stays high while a downstream rail is missing. Although this guide uses the 2015 13-inch MacBook Air A1466 logic board 820-00165 as the measured example, the same diagnostic sequence and reasoning apply broadly to Intel Macs with a separate CPU and PCH, as well as later Intel processors with the PCH integrated into the processor package. This includes Intel MacBook Pro models through 2020, such as the A2251 and A2289. The exact signal names, prerequisite rails, logic levels and timing values vary by model, so always confirm them against the correct schematic and boardview
Quick answer: what to check when PM_SLP_S4_L is missing
- Measure both sides of the signal path. A high level at the CPU/PCH side but a low level downstream indicates a resistor, buffer, trace or load problem.
- Decide whether the signal is continuously low or briefly high. If the prerequisites look correct, use an oscilloscope in single-acquisition mode.
- For a continuously low signal, work backwards. Check RTC power and reset, the 32.768 kHz clock, deep-sleep and suspend rails, BATLOW#, RSMRST# and the wake request.
- For a pulse that collapses, look downstream. Capture an S3 rail, an S0 rail and ALL_SYS_PWRGD to find the first failed event.
- For a steady high signal with a missing S3 rail, trace the enable chain. Check the series resistor, logic gate, regulator enable, regulator input and rail resistance.
Table of Contents
What is PM_SLP_S4_L?
Apple’s PM_SLP_S4_L name corresponds to Intel’s SLP_S4# sleep-state output. The suffix “_L” and the Intel “#” both indicate active-low logic. The signal is asserted when it is low and de-asserted when it rises high during the wake sequence.
Intel documents SLP_S4# as the signal used to remove power from additional subsystems that remain powered in S3 and, in particular, to control memory power cycling. On 820-00165, the de-asserted high state is approximately 3.3 V and is distributed through board logic to enable S3 rails such as PP5V_S3, PP3V3_S3, PP1V8_S3 and PP1V2_S3. PM_SLP_S3_L then releases the S0 portion of the sequence.
This active-low wording matters. During power-on, the important event is that the CPU/PCH de-asserts the sleep signal high, allowing the downstream enable chain to proceed.
Which Mac does this example cover?
The principal example is the MacBook Air A1466 (Early 2015), logic board 820-00165. Apple lists the base machine with a 1.6 GHz Intel Core i5, and Intel identifies the i5-5250U as a 5th-generation Broadwell processor. This corrects the old description of this board as Haswell.
The diagnostic method is also useful on many earlier Intel MacBook and MacBook Pro designs, but signal names, pull-ups, logic levels and rail order can vary. Always confirm the exact schematic and boardview for the board under repair.
Intel Mac power states in practical board-repair terms
| State | Practical meaning | Typical repair focus |
|---|---|---|
| G3 | Mechanical-off / minimum always-on state | RTC and always-on foundations; charger, SMC and PPBUS creation |
| S5 | Soft-off / standby state | PP3V3_S5, the deep-sleep well, DPWROK and resume-reset preparation |
| S4 | Hibernate context | SLP_S4# controls the boundary into memory-related S3 power |
| S3 | Suspend-to-RAM context | S3 rails and memory are powered; SLP_S3# controls the move towards S0 |
| S0 | Fully on | S0 rails, ALL_SYS_PWRGD, CPU core power, clocks, reset release and firmware execution |
These names are most useful as schematic domains. Later Intel and Apple silicon platforms require their own board-specific sequence.
The practical 11+1 checklist for 820-00165
Technicians often describe the older Intel checklist as 11 readiness conditions plus one wake request. It is a practical board-level method, not an Intel-published universal count. Confirm the exact net names and levels against the schematic for the board being repaired.
| Checkpoint | Expected on 820-00165 | Why it matters |
|---|---|---|
| PPVRTC_G3H (VCCRTC) | Approximately 3.3 V | Powers the RTC well. A weak or missing rail prevents reliable reset and wake logic. |
| RTC_RESET_L (RTCRST#) | High | Releases the primary RTC-well reset. |
| PCH_SRTCRST_L (SRTCRST#) | High | Releases the secondary RTC / management-well reset. |
| PCH_INTVRMEN / board-named variant | Valid strap state | Selects the intended internal or external suspend-regulator configuration. |
| PCH_DSWVRMEN / board-named variant | Valid strap state | Selects the intended deep-sleep-well regulator configuration. |
| SYSCLK_CLK32K_RTCX1 | 32.768 kHz present | Provides the RTC timebase. Use a high-impedance oscilloscope; do not expect a 3.3 V square wave at the crystal input. |
| PP3V3_S5 | Approximately 3.3 V | Supplies the deep-sleep well and associated logic. |
| PM_DSW_PWRGD (DPWROK) | High | Reports that the deep-sleep supply is valid. |
| PP3V3_SUS | Approximately 3.3 V | Supplies the suspend well required before resume-reset release. |
| PM_BATLOW_L (BATLOW#) | High / not asserted | A low battery indication can inhibit wake from S3-S5. |
| PM_RSMRST_L (RSMRST#) | High | Confirms that the suspend domain is ready for the wake sequence. |
| PM_PWRBTN_L or SMC_ADAPTER_EN | Low-going button pulse or valid adapter auto-power request | Provides the “+1” wake event. |
Recommended measurement order
| Order | Measurement group | Decision |
|---|---|---|
| 1 | PPVRTC_G3H, RTCRST#, SRTCRST# and the 32.768 kHz RTC clock | If any are wrong, repair the RTC foundation first. |
| 2 | PP3V3_S5 and PM_DSW_PWRGD | If absent or unstable, remain in the deep-sleep section. |
| 3 | PP3V3_SUS and PM_RSMRST_L | If suspend power is missing, do not expect a valid wake release. |
| 4 | PM_BATLOW_L and the wake request | Confirm that the PCH is permitted and requested to wake. |
| 5 | PM_SLP_S4_L and PM_SLP_S3_L | Classify the fault as steady low, pulse-and-collapse or valid high. |
| 6 | S3/S0 rails, ALL_SYS_PWRGD, CPU core and SPI activity | Find the first event that fails after the sleep outputs rise. |
Reference power-on timing captured on a working 820-00165
This laboratory capture used a working board with the charger connected and the battery disconnected. Zero milliseconds is the moment PPBUS_G3H first appears. Treat the numbers as a diagnostic reference rather than a universal specification.
| Approx. time | Signal or rail | Observed event | Diagnostic meaning |
|---|---|---|---|
| 0 ms | PPBUS_G3H | Created at about 8.1 V | Main system bus becomes available. |
| 200 ms | PPBUS_G3H | Adjusted to about 8.6 V | SMC and charging control are communicating and regulating the bus. |
| 350 ms | PP3V3_S5 | Rises to 3.3 V | Deep-sleep / standby power becomes available. |
| 780 ms | PM_RSMRST_L | De-asserts high | Suspend domain reports ready for wake. |
| About 788 ms | PM_SLP_S4_L and PM_SLP_S3_L | De-assert high in close succession | PCH releases the S3 and S0 power sections. |
| 790 ms | PP1V2_S3 | Memory rail appears | The S3 memory-power path responded to PM_SLP_S4_L. |
| 791 ms | PP1V05_S0 | Core-well / bus rail appears | An early S0 rail responded to PM_SLP_S3_L. |
| 800 ms | ALL_SYS_PWRGD | Rises high | Monitored S3 and S0 rails have passed validation. |
| Around 800 ms | PPBUS_G3H | Brief load-related dip, then recovery | Normal transient as several rails start together, provided recovery is clean. |
| 805 ms | PPVCC_S0_CPU | CPU core rail appears | The sequence reaches CPU core power. |
Three PM_SLP_S4_L fault patterns
| What you see | What it usually means | Where to go next |
|---|---|---|
| 0 V continuously | The wake sequence was not permitted, not requested or not reached; alternatively, the net is held low. | Check the 11+1 conditions, isolate pull-downs and compare the CPU/PCH side with the downstream side. |
| Short 3.3 V pulse | The sequence started but a later validation failed, so the platform returned to sleep. | Scope S3/S0 rails, ALL_SYS_PWRGD and SPI activity. Find the first absent or collapsing event. |
| Steady 3.3 V but an S3 rail is missing | The CPU/PCH output is valid; the fault is in the fan-out, enable logic, regulator or load. | Trace through the resistor or buffer to the regulator enable and check rail resistance. |
| High at source, low after a resistor or logic gate | Open or corroded trace, failed series component, damaged gate or downstream pull-down. | Repair the signal path; do not condemn the CPU/PCH. |
Why an oscilloscope matters
A multimeter is ideal for identifying a stable logic level, but it averages fast changes. In a restart loop, PM_SLP_S4_L may rise to approximately 3.3 V for only 120-127 ms and then return low. Depending on the meter’s sample rate, the display may remain at 0 V or show only an unstable flicker.
Use a high-impedance probe, a clean nearby ground and single-acquisition triggering on the rising edge of PM_SLP_S4_L. Capture at least one S3 rail, one S0 rail and ALL_SYS_PWRGD. The objective is to identify the first downstream event that fails before the pulse collapses.
Case Study 1 — A1278 2011, 820-2936: weak PPVRTC_G3H
Fault: The water-damaged board had PP3V3_S5 but no PP5V_S3. The PP5V_S3 enable chain led back to PM_SLP_S4_L, which was low.
Finding: PPVRTC_G3H measured only about 1.5 V instead of the expected 3.3 V. That weak RTC supply prevented the PCH RTC domain from reaching a valid operating condition.
Repair: Light corrosion was found around clock chip U2800. Replacing U2800 restored PPVRTC_G3H and the board completed the power-on sequence.
Lesson: The stronger diagnosis is that U2800 failed to provide a valid RTC-domain supply, so the PCH could not release the sleep signal. The same symptom could also result from a pull-down or damaged trace elsewhere on PPVRTC_G3H.
Case Study 2 — A1502 2015, 820-4924: PM_BATLOW_L held low
Fault: The board had PP3V3_S5 but no PP5V_S3. PM_SLP_S4_L was 0 V, and the prerequisite check found PM_BATLOW_L at only 0.9 V.
Finding: R1410 measured 10 kΩ and its PP3V3_S5_PCH_GPIO pull-up supply was present. Removing Q3000 did not release the line. The remaining possible pull-down paths were the SMC and CPU/PCH sides.
Repair: The SMC was isolated and the line was tested using a current-limited, board-appropriate pull-up method. PM_BATLOW_L then rose normally, showing that the CPU/PCH side was not dragging it down. A reballed SMC from the correct donor board restored normal operation.
Lesson: BATLOW# is not an informational signal only. An asserted BATLOW# can inhibit waking from S3-S5. Diagnose the pull-up and every possible open-drain pull-down before replacing the CPU/PCH.
Case Study 3 — A1466 2015, 820-00165: PP3V3_SUS missing
Fault: The clean board had PP3V3_S5 but no PP5V_S3. PM_SLP_S4_L remained low.
Finding: The 11+1 check showed PP3V3_SUS at about 0.1 V. U8020 had a valid 3.3 V input and a valid P3V3SUS_EN command, but no correct output.
Repair: Replacing the U8020 suspend-rail switch restored PP3V3_SUS and the full power-on sequence.
Lesson: A missing PM_SLP_S4_L signal can be a consequence of a failed suspend rail. Once U8020’s input and enable were confirmed, the diagnosis did not require replacing the SMC, clock chip or CPU.
Case Study 4 — A1466 2013, 820-3437: the signal was pulsing, not missing
Test setup: A working board was deliberately given an SPI communication fault by holding SPI_MLBROM_CS_L low. This controlled test shows what a post-power-on boot failure does to PM_SLP_S4_L.
Oscilloscope result: PM_RSMRST_L rose at about 780 ms. PM_SLP_S4_L and PM_SLP_S3_L then rose at about 788 ms, followed by memory and S0 rails, ALL_SYS_PWRGD and CPU core power. Because the SPI path could not complete the required boot read, PM_SLP_S4_L returned low at about 915 ms. The board retried after roughly 4.25 seconds.
Lesson: A multimeter reading of 0 V did not mean the PCH never released PM_SLP_S4_L. The signal existed briefly and was withdrawn because a later stage failed. When all readiness conditions are present, a scope capture is safer and more informative than jumping directly to CPU/PCH replacement.
Common mistakes to avoid
Calling the CPU/PCH faulty from one DC reading
A single 0 V reading cannot distinguish a genuinely absent output from a short pulse, a pulled-down net or a broken path between the CPU/PCH and the test point.
Measuring only at the downstream regulator
A missing regulator-enable voltage may result from an open resistor, failed logic gate or corroded via even when PM_SLP_S4_L is correct at the source. Compare both sides of every series component.
Using the 820-00165 checklist as a universal specification
The principle transfers; the exact names and voltages do not. Sixth-generation and later Intel designs, T1/T2 Macs and Apple silicon Macs require their own board-specific sequence.
Forcing power-good signals as a routine test
Do not short ALL_SYS_PWRGD or another power-good net as a normal troubleshooting shortcut. Forcing validation signals can mask the original fault, hold defective rails on and create additional risk. Use oscilloscope correlation and current-limited, board-specific isolation methods instead.
Related older Intel Mac power-sequence guides
Previous: MacBook SMC circuit and PPBUS_G3H voltage adjustment
Next: MacBook logic board power rails and ALL_SYS_PWRGD
Conclusion
When PM_SLP_S4_L is missing on an older Intel MacBook, first confirm the RTC, deep-sleep, suspend, battery-permission, resume-reset and wake-request conditions. Then determine whether PM_SLP_S4_L is continuously low, briefly high or valid while a downstream rail is absent.
That distinction turns one symptom into three different diagnostic paths. It prevents unnecessary SMC or CPU/PCH replacement and keeps the repair focused on the first point where the measured sequence departs from the expected one.
For newer platforms, see our Apple silicon Mac logic-board repair case studies.
