This article is for MacBook logic board component-level repair professionals, written by IT-Tech Online, the MacBook repair specialist in Melbourne, Australia.
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We will discuss MacBook power sequences from CPU/PCH shoots out PM_SLP_S5_L to all system power rails (except CPU power rail) are present. We will use the MacBook Air 13” 2015-2017 logic board schematics 820-00165 as references.
Note: These S3 power rails are not created at the same time. The RC delay circuits are used to control the delay time, therefore the timing. By changing the values of resistors and capacitors, we can get the delay time as we want.
Note: These S0 power rails are not created at the same time. The timing is determined by the PM_SLP_S3_L control signal and the associated RC delay circuits.
Apple has developed a complex validation mechanism to ensure all the power rails being created are stable and good (GD stands for good) for use. If all the power rails are good, then a valid ALL_SYS_PWRGD signal will be produced. ALL_SYS_PWRGD voltage is 3.3V.
A valid ALL_SYS_PWRGD signal checks these power rails: PP1V8_S3, PP5V_S3, PP1V2_S3, PP1V05_S0, PP5V_S0, PP3V3_S0, PP1V5_S0. Any of these S3 or S0 state power rails malfunction will pull down the ALL_SYS_PWRGD signal and terminate the normal power-up process of Apple computers.
The ALL_SYS_PWRGD signal will be reported to SMC. SMC will process this signal and prepare to create the last power rail – CPU/PCH Vcore power rail.