MacBook Logic Board Power Rails: S3, S0 and ALL_SYS_PWRGD
This component-level guide explains the Intel MacBook power sequence from the S5/S4 handoff through the S3 and S0 logic-board power rails to a valid ALL_SYS_PWRGD signal. It uses the 2015–2017 13-inch MacBook Air A1466 logic-board diagram and 820-00165 schematic as the principal reference.
Quick answer
During power-up, the active-low Intel sleep signals are released high in order. PM_SLP_S4_L distributes the S3 enables for PP3V3_S3, PP1V8_S3, the DDR 1.2 V rail and related loads. PM_SLP_S3_L is then qualified by PP3V3_S5 through U8180 to create PM_SLP_S3_BUF_L, which fans out the S0 enables. ALL_SYS_PWRGD can rise to approximately 3.3 V only after the monitored S3 and S0 rails and their power-good signals are valid.
This page focuses on the rail sequence after the SMC and CPU/PCH startup prerequisites are satisfied, but before CPU Vcore is created. The same diagnostic method applies to many Intel Macs; rail names, regulator designators, RC delays and the exact ALL_SYS_PWRGD contributors vary by model.
Previous guide: PM_SLP_S4_L timing and fault patterns. Next guide: CPU Vcore and PPVCC_S0_CPU creation. Apple silicon Macs use a substantially different PMU, embedded-SMC and SoC power architecture. See the complete M1 Pro A2442 820-02098 power-on sequence and Apple silicon logic-board repair case studies.
Table of Contents
What this MacBook logic-board diagram covers
The 820-00165 schematic divides the Intel MacBook power sequence into power states. Each state adds rails and devices while retaining the rails required from the previous state. The suffix _L identifies an active-low signal; during power-up, PM_SLP_S5_L, PM_SLP_S4_L and PM_SLP_S3_L normally rise high as the system exits those sleep states.
Do not start with ALL_SYS_PWRGD. Locate the first missing sleep signal, enable, source rail, output rail or PGOOD input in sequence.
Intel Mac power states at a glance
| Stage | Main transition signal | Important results on 820-00165 | Diagnostic meaning |
|---|---|---|---|
| S5 standby | SMC_PM_G2_EN → S5_PWR_EN | U7501 standby regulator operating; PP3V3_S5 and PP5V_S4RS3 available | The SMC has enabled the early standby stage. |
| Exit S5 / enter S4 | PM_SLP_S5_L rises high | S4_PWR_EN path and S4-domain switches can become active | The CPU/PCH permits the board to leave the deeper sleep state. |
| Exit S4 / enter S3 | PM_SLP_S4_L rises high | P3V3S3_EN, P1V8S3_EN, DDRREG_EN and USB_PWR_EN | The S3 regulator and load-switch sequence begins. |
| S3 rails valid | S3 enables and regulator soft-start | PP3V3_S3, PP1V8_S3, PP1V2_S3 and related device power | Memory and other S3-domain circuits are powered. |
| Exit S3 / enter S0 | PM_SLP_S3_L rises; U8180 creates PM_SLP_S3_BUF_L | P5VS0_EN, P3V3S0_EN, P1V05S0_EN and other S0 enables | The fully-on S0 rail sequence begins. |
| S0 rails valid | S0 regulators and switches report valid output | PP5V_S0, PP3V3_S0, PP1V05_S0 and PP1V5_S0 | The non-Vcore system rails have reached their valid ranges. |
| System validation | All PGOOD contributors release the common node | ALL_SYS_PWRGD rises to approximately 3.3 V | The SMC can continue toward delayed power-good and CPU Vcore. |
1. S5 and S4 establish the standby sources
The preceding SMC guide ends with SMC_PM_G2_EN. On 820-00165, it passes through R8140 as S5_PWR_EN and starts the standby regulator stage. U7501 is a dual buck controller associated with the 5 V and 3.3 V standby domains, including PP5V_S4RS3 and PP3V3_S5.
When PM_SLP_S5_L rises, the board can create S4_PWR_EN through the standby-enable logic. This is an earlier transition than PM_SLP_S4_L. A page that starts directly at the S3 rails can miss a failed S5/S4 source that prevents every later rail.
2. PM_SLP_S4_L fans out the S3 enables
After PM_SLP_S4_L rises high, the 820-00165 enable network distributes that signal through separate branches:
- R8112 produces P3V3S3_EN for the PP3V3_S3 switch.
- R8116 produces P1V8S3_EN for the 1.8 V S3 regulator.
- R8111, 20 kΩ produces DDRREG_EN for the DDR 1.2 V supply.
- R8117 contributes to USB_PWR_EN for the USB power-switch path.
The associated capacitors, regulator soft-start functions and load-switch behaviour create controlled delays, so the S3 rails do not appear at exactly the same moment.
Naming correction: PP5V_S4RS3 is already available through the S4/S3 portion of this design. It should not be renamed PP5V_S3 merely because its PGOOD is one of the later ALL_SYS_PWRGD contributors.
3. The principal S3 rails and expected voltages
| Enable | Rail or function | Expected | If missing |
|---|---|---|---|
| P3V3S3_EN | PP3V3_S3 | 3.3 V | Check the PP3V3_S5 source, U8010/load switch, enable and output load. |
| P1V8S3_EN | PP1V8_S3 | 1.8 V | Check the enable RC branch, regulator input and resistance to ground. |
| DDRREG_EN | PP1V2_S3 / DDR supply | Approximately 1.2 V | Check R8111, the DDR regulator, its source rail and memory-side load. |
| USB_PWR_EN | USB VBUS switch path | 5 V when enabled | Check the standby/S3 USB enable logic, switch input and port loading. |
If PM_SLP_S4_L is high but every S3 rail is absent, check the common source and schematic routing before diagnosing several regulators independently. If only one branch is missing, compare that branch’s enable voltage, RC components, regulator input, output and PGOOD.
4. PM_SLP_S3_L and U8180 create the S0 enables
PM_SLP_S3_L passes through R8178 to U8180. U8180 is an AND gate, not merely a stronger copy of the sleep signal: it qualifies PM_SLP_S3_R_L with PP3V3_S5. When both inputs are high, its output becomes PM_SLP_S3_BUF_L.
The buffered signal provides the fan-out for P5VS0_EN, P3V3S0_EN, P1V05S0_EN and related S0 control paths. It also supplies the pull-up source for ALL_SYS_PWRGD through R8167, ensuring that the final power-good signal cannot rise before the S0 transition is valid.
5. The principal S0 rails and expected voltages
| Enable or path | Rail | Expected | Role in ALL_SYS_PWRGD |
|---|---|---|---|
| P5VS0_EN | PP5V_S0 | 5 V | Q8150 monitors it through the 5 V divider. |
| P3V3S0_EN | PP3V3_S0 | 3.3 V | Q8150 monitors it through the 3.3 V divider. |
| P1V05S0_EN | PP1V05_S0 | 1.05 V | P1V05S0_PGOOD joins the common validation node. |
| Separate S0 regulator path | PP1V5_S0 | 1.5 V | Q8150 directly monitors this rail’s threshold path. |
When PM_SLP_S3_L is high but PM_SLP_S3_BUF_L is low, check R8178, both U8180 inputs, PP3V3_S5 and U8180 itself. When the buffer is high but one S0 rail is absent, move to that rail’s individual enable and regulator circuit.
6. How the ALL_SYS_PWRGD circuit works
ALL_SYS_PWRGD is a shared validation signal, not a power rail created by a single regulator. On 820-00165, several open-drain or power-good contributors must release the common node before R8167 can pull it high from PM_SLP_S3_BUF_L.
The direct PGOOD contributors include:
- PP1V8S3_PGOOD through R8166.
- P5VS4RS3_PGOOD through R8165.
- P1V05S0_PGOOD through R8164.
- DDRREG_PGOOD through R8168.
Q8150 provides analogue threshold monitoring for PP5V_S0, PP3V3_S0 and PP1V5_S0. If any monitored rail or PGOOD input is invalid, the validation node is held low. When every contributor is valid, ALL_SYS_PWRGD rises through R8162 to approximately 3.3 V.
7. What a valid ALL_SYS_PWRGD proves
A stable high ALL_SYS_PWRGD proves that the monitored S3 and S0 validation paths are released at that moment. It does not prove that CPU Vcore, system clocks, platform reset, memory training or POST have completed.
The SMC reads ALL_SYS_PWRGD and, after its required delay and other conditions, participates in the next CPU-power stage. Continue with the CPU Vcore guide if ALL_SYS_PWRGD is correct but PPVCC_S0_CPU is missing.
Recommended measurement order
| Order | Measure | Expected on 820-00165 | If missing or wrong |
|---|---|---|---|
| 1 | SMC_PM_G2_EN | High, approximately 3.3 V | Return to the SMC startup prerequisites. |
| 2 | S5_PWR_EN | High after R8140 | Check R8140, C8142 and loading on the enable path. |
| 3 | PP3V3_S5 | 3.3 V | Check U7501, its source and the S5 enable/PGOOD path. |
| 4 | PP5V_S4RS3 | 5 V | Check U7501, its 5 V channel and the load. |
| 5 | PM_SLP_S5_L and S4_PWR_EN | High during transition toward S4/S3 | Return to CPU/PCH prerequisites and U8170 standby-enable logic. |
| 6 | PM_SLP_S4_L | High, approximately 3.3 V | Use the PM_SLP_S4_L prerequisite and pulse-pattern guide. |
| 7 | P3V3S3_EN / PP3V3_S3 | High enable / 3.3 V rail | Check R8112, the source, U8010 and output loading. |
| 8 | P1V8S3_EN / PP1V8_S3 | High enable / 1.8 V rail | Check R8116 branch, regulator input and output. |
| 9 | DDRREG_EN / PP1V2_S3 | High enable / approximately 1.2 V | Check R8111, DDR regulator, memory load and DDRREG_PGOOD. |
| 10 | PM_SLP_S3_L | High, approximately 3.3 V | Check the S3 rails and CPU/PCH transition prerequisites. |
| 11 | U8180 inputs and PM_SLP_S3_BUF_L | Both inputs high; output approximately 3.3 V | Check R8178, PP3V3_S5, U8180 and output loading. |
| 12 | P5VS0_EN / PP5V_S0 | High enable / 5 V rail | Check enable routing, switch/regulator input and load. |
| 13 | P3V3S0_EN / PP3V3_S0 | High enable / 3.3 V rail | Check enable routing, source, switch and load. |
| 14 | P1V05S0_EN / PP1V05_S0 | High enable / 1.05 V rail | Check the regulator, input rail, load and PGOOD. |
| 15 | PP1V5_S0 | 1.5 V | Check its regulator path and Q8150 monitor input. |
| 16 | Four direct PGOOD inputs | Released/high when their rails are valid | Trace the first low PGOOD back to its regulator or load. |
| 17 | Q8150 divider inputs | Correct divided voltages from the three S0 rails | Check rail voltage, divider resistors, capacitors and Q8150. |
| 18 | ALL_SYS_PWRGD | Stable high, approximately 3.3 V | Check R8167, R8162, every PGOOD contributor and output loading. |
Four common power-rail fault patterns
| What you see | What it usually means | Where to go next |
|---|---|---|
| PM_SLP_S4_L is high, but one or more S3 rails are absent | The S3 enable branch, source rail, regulator or load has failed. | Compare each enable with its output and PGOOD; start with the first missing branch. |
| S3 rails are valid, but PM_SLP_S3_BUF_L is low | PM_SLP_S3_L, PP3V3_S5 or U8180 is not satisfying the AND-gate condition. | Measure both U8180 inputs, its output and resistance on PM_SLP_S3_BUF_L. |
| All named rails measure correctly, but ALL_SYS_PWRGD is low | A PGOOD input, Q8150 threshold path, pull-up component or output load is still holding the node down. | Measure each contributor directly rather than relying only on nominal rail voltage. |
| ALL_SYS_PWRGD pulses high and then falls | A rail or PGOOD becomes valid briefly and then collapses, or the timing/load causes a restart. | Use an oscilloscope to capture each rail and its PGOOD against ALL_SYS_PWRGD. |
Common diagnostic mistakes
- Treating an _L signal as if it must stay low: during power-up, the active-low sleep signals are released high as the board exits each state.
- Calling PP5V_S4RS3 “PP5V_S3”: use the model-specific schematic net name so the correct source and PGOOD are traced.
- Testing only output rails: compare source, enable, output and PGOOD at every stage.
- Assuming ALL_SYS_PWRGD comes from one IC: it is a shared validation node with several contributors.
- Replacing the CPU/PCH too early: prove the first missing sleep signal, enable or PGOOD path before selecting a major BGA device.
Related Intel and Apple silicon guides
For the conditions that produce the S3 sleep signal, read PM_SLP_S4_L timing and fault patterns. If ALL_SYS_PWRGD is stable but CPU power is missing, continue to CPU Vcore and PPVCC_S0_CPU creation. For modern repairs, browse the Apple silicon Mac logic-board case studies.
Conclusion
The reliable way to diagnose MacBook logic-board power rails is to follow the state sequence: S5/S4 sources, PM_SLP_S4_L and the S3 rails, PM_SLP_S3_L and the S0 rails, then every ALL_SYS_PWRGD contributor. On 820-00165, the common PGOOD node combines direct regulator status, Q8150 analogue monitoring and the PM_SLP_S3_BUF_L pull-up. Finding the first signal that fails turns a broad no-power symptom into a specific circuit section.
