MacBook Pro A2141 820-01700 GPU Disable Conversion

Removing LA750, LA850, LA860, LA870 and LA950 isolated the shorted AMD GPU and VRAM loads and cleared the PPBUS_G3H short.

However, removing the output inductors alone is not sufficient for the permanent conversion. Every AMD regulator enable must also be disconnected, and the genuine regulator PGOOD returns must be isolated before simulated PGOOD signals are created.

The complete GPU enable and PGOOD network is shown on schematic page 116.

1. Isolate the Shorted AMD GPU and VRAM Loads

The following inductors were shorted on their GPU or VRAM load sides:

• LA750
• LA850
• LA860
• LA870
• LA950

All five inductors were removed.

After their removal:

• The PPBUS_G3H short cleared
• The shorted GPU and VRAM loads were isolated
• PPBUS_G3H returned to a normal condition
• The CPU, onboard SSD and customer-data circuits were no longer being held down by the failed GPU subsystem

2. Retain U9801 as the GPU Sequence Controller

U9801 must remain in circuit because it controls more than the dedicated GPU.

Its functions include:

• EG_VR0–EG_VR4 enable sequencing
• GPU PGOOD monitoring
• PM_ALL_GPU_PGOOD generation
• Display-control signals
• Panel-power control
• Backlight-control signals
• I2C display management

The conversion therefore allows U9801 to produce its normal GPU enable sequence, but prevents those enables from reaching the physical AMD voltage regulators.

3. Disable Every Physical AMD GPU Rail

Remove the five 0 Ω series enable resistors between U9801 and the AMD GPU voltage regulators.

According to the schematic:

• Pin 1 is the U9801 side
• Pin 2 is the physical regulator side
• RB900–RB904 are all 0 Ω series resistors

After their removal:

• U9801 can still produce its normal EG_VR0_EN through EG_VR4_EN sequence
• None of the enable signals reaches the AMD GPU regulators
• The GPU regulators remain disabled
• Every physical AMD GPU output rail should remain at 0 V

Confirm that the regulator-side pads remain low during startup before continuing.

4. Isolate the Genuine Regulator PGOOD Signals

The real PGOOD signals from the disabled GPU regulators must not remain connected to the U9801 PGOOD inputs.

Remove the following components:

RB918 and RB919

The pin-2 ends of RB918 and RB919 join at the EG_VR3_PGOOD input to U9801.

Their regulator-source sides must remain separate. Do not connect the original GPU-core and GPU-SOC PGOOD outputs together.

RB920 and RB921

The pin-2 ends of RB920 and RB921 join at the EG_VR4_PGOOD input to U9801.

Their regulator-source sides must also remain separate. Do not connect the original GPU-memory PGOOD outputs together.

IMPORTANT

Only the U9801 input-side nodes are used for the simulated PGOOD signals.

The original regulator-source sides must remain isolated because the physical GPU regulators and output rails will be disabled.

5. Make Each Fake PGOOD Follow Its Corresponding Enable

Do not pull every GPU PGOOD signal permanently to 3.3 V.

Instead, make each U9801 PGOOD input follow its corresponding U9801 enable output through an approximately 10 kΩ resistor.

Install the following five resistive jumpers:

Each jumper should use approximately 10 kΩ.

The operating principle is:

U9801 asserts EG_VR0_EN.

The signal passes through the new 10 kΩ resistor.

U9801 then reads EG_VR0_PGOOD as high.

The same arrangement is repeated for VR1, VR2, VR3 and VR4.

Why Sequenced Fake PGOOD Is Better Than Permanent Pull-Ups

This arrangement preserves the basic timing relationship between each enable and its corresponding PGOOD input:

• PGOOD remains low before the sequence begins
• PGOOD rises only after its corresponding enable rises
• PGOOD falls when its corresponding enable is removed
• Each PGOOD follows the correct U9801 sequencing stage
• The arrangement more closely resembles normal regulator behaviour
• U9801 can complete its normal VR0-to-VR4 sequence without powering the failed AMD GPU

The existing 47 kΩ enable pull-down resistors R9820–R9824 should remain fitted.

These pull-downs hold both the enable outputs and the simulated PGOOD inputs low while U9801 is in reset or inactive.

Leave RB922 Installed

Do not remove RB922.

RB922 connects:

EG_VR4_PGOOD → PM_ALL_GPU_PGOOD

VR4 is the final stage of the GPU sequence.

When U9801 asserts EG_VR4_EN:

1. RB904 pin 1 rises
2. The new 10 kΩ jumper raises the joined RB920/RB921 pin-2 node
3. U9801 reads EG_VR4_PGOOD as high
4. RB922 passes the completed state to PM_ALL_GPU_PGOOD
5. The system receives confirmation that the complete GPU power sequence has finished

This allows PM_ALL_GPU_PGOOD to be generated without turning on any of the physical AMD GPU regulators.

Measurements After Completing the Modification

Before proceeding with the display conversion, confirm the following:

If any physical GPU output rail appears, stop and check RB900–RB904 isolation before continuing.

6. Connect Intel Panel Power and Backlight Enable

After the physical GPU rails were disabled and the simulated PGOOD sequence was working, the Intel display-control requests were connected to the final display paths:

EDP_IG_PANEL_PWR → EDP_PANEL_PWR_EN

EDP_IG_BKLT_EN → EDP_BKLT_EN

This produced an Intel-driven image with a dim Apple logo.

PPVOUT_S0_LCDBKLT measured approximately 54.3 V, confirming that the panel supply, backlight boost converter and LED strings were operating.

7. Force U9850 to the Intel eDP Source

U9801 was retained for its required control functions.

The U9801 side of the R9819 selection path was isolated, and the U9850 mux-side input was forced to a definite 3.3 V state.

This permanently selected Intel eDP while keeping the high-speed eDP lanes routed through U9850.

8. Confirm I2C Backlight Communication

Schematic page 81 shows U8400/LP8548B1 on the logic board.

EDP_BKLT_EN reaches U8400’s enable input through R8442. The display TCON communicates with U8400 through:

• I2C_BKLT_SCL
• I2C_BKLT_SDA

The converted board was compared with a known-good board.

At a wide timebase, both SCL and SDA showed active communication. Captures at 5 µs/div and 2 µs/div allowed individual byte frames and the ninth clock to be inspected.

During the ninth SCL-high period, SDA was low. This is a valid I2C ACK and confirms that U8400 was alive and acknowledging the TCON transaction.

The ACK ruled out:

• An open SCL or SDA trace
• U8400 being unpowered
• A continuously NACKing backlight controller
• A completely inactive TCON-to-backlight communication path

The ACK does not prove that the brightness value was identical to the value used in the original AMD-GPU configuration. It only confirms that the controller received and acknowledged the transaction.