Intel Mac CPU Vcore: PPVCC_S0_CPU Power Sequence
This component-level guide explains how an Intel Mac creates the CPU Vcore rail PPVCC_S0_CPU after the S3 and S0 power rails have passed validation. It uses the 2015–2017 13-inch MacBook Air A1466 logic board and 820-00165 schematic as the principal reference.
Quick answer
On 820-00165, ALL_SYS_PWRGD and PM_SLP_S3_L are combined by U1930 to create CPU_VCCST_PWRGD. The CPU/PCH then asserts CPU_VR_EN, enabling U7200. With PP5V_S0 at its control supply and PPBUS feeding the two-phase power stage, U7200 drives the MOSFETs and inductors that create PPVCC_S0_CPU. The CPU communicates directly with U7200 over the SVID interface, so CPU Vcore is dynamic rather than a fixed 1.9 V or 1.7 V test point.
This page begins with a stable ALL_SYS_PWRGD and ends with CPU Vcore, CPU_VR_READY, PCH power-good progression, clocks and platform reset. The diagnostic method applies broadly to Intel Macs, but controller designators, rail names, SVID generations, output phases and voltage behaviour vary by model.
Previous guide: MacBook S3/S0 power rails and ALL_SYS_PWRGD. For earlier prerequisites, see PM_SLP_S4_L timing and fault patterns. Apple silicon Macs use a substantially different PMU, embedded-SMC and SoC power architecture. See the complete M1 Pro A2442 820-02098 power-on sequence and Apple silicon Mac logic-board repair case studies.
Table of Contents
What this CPU Vcore guide covers
PPVCC_S0_CPU is the main CPU core-voltage rail on this Intel MacBook Air design. It is created late in the hardware power sequence, after S3 and S0 rails are valid. A missing PPVCC_S0_CPU therefore does not automatically indicate a failed CPU or U7200: the first task is to locate the earliest missing prerequisite.
The 820-00165 reference separates the sequence into three related paths: the CPU VCCST power-good gate, the two-phase CPU voltage regulator, and the later PCH system-power-good/reset path.
CPU Vcore sequence at a glance
| Stage | Signal or circuit | Result on 820-00165 | What it proves |
|---|---|---|---|
| System rails valid | ALL_SYS_PWRGD | Stable high, approximately 3.3 V | The monitored S3 and S0 validation paths have passed. |
| VCCST validation | ALL_SYS_PWRGD + PM_SLP_S3_L → U1930 | CPU_VCCST_PWRGD rises through the PP1V05_S0 pull-up | The CPU/PCH standby-core prerequisites are valid. |
| VR enable | CPU/PCH → CPU_VR_EN | U7200 VR_ON is driven high | The platform is requesting CPU core power. |
| Controller starts | U7200 ISL95826 | CPUVR_PWM1 and CPUVR_PWM2 switch | The controller has accepted its supplies, enable and programmed conditions. |
| Two-phase conversion | U7310/U7320, MOSFETs and L7310/L7320 | PPBUS is converted into PPVCC_S0_CPU | The high-current power stage is operating. |
| Regulator valid | CPU_VR_READY | PGOOD rises when U7200 considers the output valid | The controller reports a valid CPU rail. |
| Firmware and reset | PM_PCH_PWROK, PM_PCH_SYS_PWROK, clocks and PLT_RESET_L | The platform proceeds towards firmware execution and POST | Power creation has moved into the clock/reset stage. |
1. ALL_SYS_PWRGD and PM_SLP_S3_L create CPU_VCCST_PWRGD
U1930 is a 74AUP1G09 open-drain AND gate. Its two inputs are ALL_SYS_PWRGD and PM_SLP_S3_L. Both must be high before the output can be released.
R1931 pulls the output up from PP1V05_S0, so CPU_VCCST_PWRGD is expected near the 1.05 V domain rather than 3.3 V. U1930 itself is powered by PP3V3_S5. This makes four useful checks at the gate: PP3V3_S5, both logic inputs, and the PP1V05_S0 output pull-up.
If ALL_SYS_PWRGD is high but CPU_VCCST_PWRGD is low, do not jump directly to the CPU/PCH. Check PM_SLP_S3_L, PP1V05_S0, R1931, U1930 and resistance to ground on the output net.
2. CPU_VR_EN is the direct command to U7200
CPU_VCCST_PWRGD is delivered to the CPU/PCH power-control domain. When the remaining internal conditions are satisfied, the platform asserts CPU_VR_EN. This signal connects directly to the VR_ON input of U7200.
A missing CPU_VR_EN with valid CPU_VCCST_PWRGD points upstream of the regulator. Possible causes include missing PCH/CPU prerequisites, clock or firmware-state problems, a loaded signal, or a BGA connection fault. Replacing U7200 cannot restore an enable that never reaches its VR_ON pin.
3. U7200 requires both control power and high-current input power
U7200 is an ISL95826 two-phase Intel CPU voltage controller. On 820-00165:
- VDD is supplied from PP5V_S0 through R7201.
- VIN monitors the PPBUS_S5_HS_COMPUTING_ISNS input through R7202.
- VR_ON receives CPU_VR_EN.
- CPUVR_PWM1 and CPUVR_PWM2 control the two external power phases.
- CPU_VR_READY is the regulator power-good output.
- CPU_VIDSOUT, CPU_VIDSCLK and CPU_VIDALERT_L form the CPU-to-regulator SVID interface.
4. The two-phase power stage creates PPVCC_S0_CPU
U7200 does not carry the CPU load current itself. Its PWM outputs drive U7310 and U7320, which switch the high-side and low-side MOSFETs for phase 1 and phase 2. L7310 and L7320 combine the two phases at the PPVCC_S0_CPU output.
The high-current source is the PPBUS_S5_HS_COMPUTING_ISNS domain. If CPU_VR_EN is high and U7200 produces PWM activity but PPVCC_S0_CPU remains at 0 V, inspect the phase drivers, MOSFET gate signals, switching nodes, inductors, current-sense paths and resistance to ground on the CPU rail.
Do not probe a switching node with the same expectations as the final DC output. Use a suitable oscilloscope probe and ground connection, and compare both phases.
5. PPVCC_S0_CPU is a dynamic voltage, not a fixed 1.9 V test
The 820-00165 power-stage schematic specifies a maximum output of 1.85 V; it does not specify that the rail must remain at 1.9 V. After startup, the CPU communicates directly with U7200 over SVID and requests the voltage required for its current operating state.
Consequently, a multimeter reading varies with the boot stage, CPU model, load, sleep state and whether the sequence is stable or restarting. Diagnose the rail by correlating CPU_VR_EN, PWM activity, PPVCC_S0_CPU, CPU_VR_READY and the SVID lines. Do not use a fixed “1.9 V before VID and 1.7 V after VID” rule.
Working-board timing reference: in the previously captured 820-00165 sequence, ALL_SYS_PWRGD rose at approximately 800 ms and PPVCC_S0_CPU appeared at approximately 805 ms. Treat that 5 ms interval as a laboratory reference, not a universal specification.
6. What CPU_VR_READY does—and does not—prove
CPU_VR_READY is U7200’s PGOOD output. A stable high signal shows that the controller considers its regulated output valid. It does not prove that the CPU is executing code, that SVID communication remains healthy under load, or that the platform has released reset.
On this specific 820-00165 configuration, R1951 between CPU_VR_READY and CPUVR_PGOOD_R is marked NO STUFF. CPUVR_PGOOD_R is instead pulled high by R1950. Therefore CPU_VR_READY is not an active qualifier in U1950’s PM_PCH_PWROK gate on this board revision, even though the signal remains important at the CPU and regulator.
7. PM_PCH_PWROK and SMC_DELAYED_PWRGD are a separate branch
U1950 contains two AND gates used for PCH power-good generation. Its first gate combines ALL_SYS_PWRGD with CPUVR_PGOOD_R to create PM_S0_PGOOD. On this board, the R1950 pull-up and unstuffed R1951 make that second input effectively high, so PM_S0_PGOOD follows the valid ALL_SYS_PWRGD condition. The same node supplies PM_PCH_PWROK and APWROK to the PCH.
The second U1950 gate combines PM_S0_PGOOD with SMC_DELAYED_PWRGD. Its output passes through R1962 as PM_PCH_SYS_PWROK. SMC_DELAYED_PWRGD therefore belongs to this later PCH system-power-good path; it is not the direct signal that enables U7200 or creates CPU Vcore.
Do not assume a universal 99 ms delay. Measure the actual relationship between ALL_SYS_PWRGD, CPU_VR_EN, CPU Vcore, SMC_DELAYED_PWRGD and PM_PCH_SYS_PWROK on the board being diagnosed.
8. SVID, SPI, clocks and PLT_RESET_L
The original page incorrectly described the PCH Management Engine firmware as the source of CPU voltage IDs. On this design, the schematic shows the CPU connected directly to U7200 through the SVID signals. The PCH SPI/ME firmware path is important for platform initialization, but it is separate from the direct CPU-to-regulator voltage-control interface.
After the required power-good inputs are valid, the PCH can progress through SPI activity, clock configuration and reset sequencing. PLT_RESET_L is an important milestone, but its presence does not mean macOS has started; it means the platform has advanced beyond the main power-rail creation stage. Verify its board-specific logic-high level rather than assuming a universal 1.05 V value.
Recommended measurement order
| Order | Measure | Expected on 820-00165 | If missing or wrong |
|---|---|---|---|
| 1 | ALL_SYS_PWRGD | Stable high, approximately 3.3 V | Return to the S3/S0 rail and PGOOD validation page. |
| 2 | PM_SLP_S3_L | High during the S0 transition | Check S3 rails and CPU/PCH sleep-state prerequisites. |
| 3 | PP3V3_S5 and PP1V05_S0 | 3.3 V and 1.05 V | Restore the source rail before testing U1930. |
| 4 | U1930 inputs | ALL_SYS_PWRGD and PM_SLP_S3_L both high | Trace the first low input upstream. |
| 5 | CPU_VCCST_PWRGD | High near the PP1V05_S0 pull-up level | Check U1930, R1931, PP1V05_S0 and output loading. |
| 6 | CPU_VR_EN at U7200 VR_ON | Logic high | Check the CPU/PCH control path and signal loading. |
| 7 | U7200 VDD | Approximately 5 V from PP5V_S0 | Check R7201, PP5V_S0 and local decoupling. |
| 8 | U7200 VIN / PPBUS source | Main PPBUS present at the CPU VR input path | Check R7202, PPBUS and high-side current-sense routing. |
| 9 | CPUVR_PWM1 and CPUVR_PWM2 | Switching activity after CPU_VR_EN | Check U7200 programming, NTC, enable, supply and fault conditions. |
| 10 | Phase-driver outputs and switch nodes | Both phases switching | Check U7310/U7320, MOSFETs, bootstrap components and gate paths. |
| 11 | L7310/L7320 and PPVCC_S0_CPU | Combined dynamic CPU core voltage | Check inductors, sense paths, output capacitors and resistance to ground. |
| 12 | CPU_VR_READY | Stable high when the regulator output is valid | Look for rail error, collapse, controller fault or output loading. |
| 13 | SVID signals | Digital activity during CPU voltage negotiation | Check signal integrity, CPU connection and U7200 interface. |
| 14 | SMC_DELAYED_PWRGD | Transitions high later in the platform sequence | Check SMC prerequisites and whether the sequence is restarting. |
| 15 | PM_PCH_SYS_PWROK | High when both U1950 gate inputs are valid | Check U1950, R1962, PM_S0_PGOOD and SMC_DELAYED_PWRGD. |
| 16 | SPI clocks and PLT_RESET_L | Activity followed by reset release | Move to firmware, clock, reset and POST diagnosis. |
Five common CPU Vcore fault patterns
| What you see | What it usually means | Where to go next |
|---|---|---|
| ALL_SYS_PWRGD is high, but CPU_VCCST_PWRGD is low | PM_SLP_S3_L, PP1V05_S0, U1930, R1931 or the output load is wrong. | Measure both gate inputs, gate supply, pull-up source and output resistance. |
| CPU_VCCST_PWRGD is high, but CPU_VR_EN is absent | The CPU/PCH has not accepted another internal prerequisite or the enable net is loaded. | Check clocks, reset prerequisites, firmware state and the CPU/PCH connection. |
| CPU_VR_EN is high, but there is no PWM activity | U7200 lacks VDD/VIN, detects a programmed fault, or is defective. | Check PP5V_S0, PPBUS, NTC/programming networks and both PWM pins. |
| PWM activity is present, but PPVCC_S0_CPU is 0 V | The phase driver, MOSFET, inductor, sense path or output load has failed. | Compare both phases and test rail resistance before replacing the CPU. |
| PPVCC_S0_CPU appears briefly and collapses | The rail is overloaded, a phase is failing, SVID negotiation stops, or the platform restarts. | Capture CPU_VR_EN, PWM, Vcore, CPU_VR_READY and ALL_SYS_PWRGD together. |
What abnormal charger current reveals during PCH and CPU startup
Charger input current can help identify how far an Intel Mac logic board progresses through its power-on sequence. However, the current reading is meaningful only when it is correlated with power rails and control signals.
The following observations were captured on a MacBook Air A1466 logic board, board number 820-00165, with the battery disconnected. They are useful diagnostic examples, but they should not be treated as universal pass-or-fail current values. Current consumption varies with the Mac model, processor, connected devices, charger and the exact fault.
SPI ROM failure and repeated startup attempts
In this capture, a fault on the SPI ROM chip-select path caused the charger current to fluctuate between approximately 0.028A and 0.033A.
The oscilloscope timeline shows that:
The PCH begins attempting to access the SPI ROM at approximately 800.5ms.
PPVCC_S0_CPUappears at approximately 805ms.The PCH withdraws
PM_SLP_S3_Lat approximately 915ms after the firmware-reading process fails.PPVCC_S0_CPUdisappears at approximately 919ms.Another startup attempt begins at approximately 4.25 seconds.
This is not the behaviour of a completely inactive board. The logic board reaches the CPU power stage briefly, attempts to read its firmware and then shuts down because the startup process cannot continue.
A multimeter or charger-current display may show only a small fluctuating current. An oscilloscope is required to reveal the brief appearance of CPU Vcore and the subsequent withdrawal of the PCH sleep signal.
Controlled fault observations
| Test condition | Observed charger current | Power stage reached | Diagnostic meaning |
|---|---|---|---|
| SPI ROM chip-select path held low | Approximately 0.028–0.033A, fluctuating | Brief firmware-read and CPU-power attempt | The PCH attempts to read the SPI ROM, fails and withdraws PM_SLP_S3_L. The board then retries the sequence. |
ALL_SYS_PWRGD held low | Approximately 0.128A and stable | S0 rails present, but PPVCC_S0_CPU absent | The sequence stops before CPU core power. Check the power-good inputs that contribute to ALL_SYS_PWRGD, followed by CPU_VR_EN and the CPU regulator circuit. |
PM_PCH_PWROK held low | Approximately 0.231A and stable | S0 rails and CPU Vcore present | The CPU regulator has started successfully. The sequence is being blocked after CPU Vcore generation, at the PCH power-good or firmware-progression stage. |
CPU_VCCST_PWRGD or PM_PCH_SYS_PWROK held low | Approximately 0.028–0.033A, fluctuating | PCH still attempts SPI access before shutdown | A similar low-current cycling pattern can be produced by different downstream faults. Current alone cannot identify the failed signal. |
What the R6117 isolation test indicates
The test record states that removing R6117 allowed the logic board to complete startup. No activity was observed on SPI_SMC_CS_L during the normal cold-start sequence.
This indicates that isolating the SMC-side SPI chip-select branch removed the condition that was preventing startup. However, the observation does not prove that the circuit is used only for SMC firmware updates. That remains a working hypothesis unless it can be confirmed by additional captures or circuit documentation.
The important diagnostic result is that the main SPI ROM could still support a normal boot after the SPI_SMC_CS_L branch was isolated.
Do not diagnose from current alone
Several different faults can produce almost identical charger-current readings. A reading of approximately 0.03A, for example, does not automatically prove that the SPI ROM, PCH or CPU is faulty.
For a restarting A1466 board, compare the charger current with at least these signals:
PM_SLP_S4_LPM_SLP_S3_LALL_SYS_PWRGDCPU_VR_ENPPVCC_S0_CPUCPU_VCCST_PWRGDPM_PCH_PWROKPM_PCH_SYS_PWROKSPI_MLB_CS_L
The signal that disappears first normally provides more useful diagnostic information than the average charger-current reading.
Important: The forced-low tests above were controlled fault-injection experiments. Do not deliberately short power-good or SPI signals on a customer’s logic board. Measure the naturally occurring signals and compare their timing instead.
Oscilloscope setup for a restarting board
Use single-acquisition triggering on the rising edge of CPU_VR_EN or PPVCC_S0_CPU. A useful four-channel capture is CPU_VR_EN, one PWM or switch-node signal, PPVCC_S0_CPU and CPU_VR_READY. Repeat with ALL_SYS_PWRGD or SMC_DELAYED_PWRGD if the entire power sequence collapses.
A static multimeter can average a short pulse into a misleading low voltage. The sequence order is more valuable than one isolated number.
Corrections to the earlier explanation
- CPU Vcore is not directly controlled by SMC_DELAYED_PWRGD: CPU_VR_EN is the direct U7200 command; SMC_DELAYED_PWRGD qualifies the later PM_PCH_SYS_PWROK branch.
- CPU voltage IDs do not come from ME firmware through the PCH: the CPU communicates directly with U7200 over SVID.
- PPVCC_S0_CPU is not a fixed 1.9 V or 1.7 V diagnostic: the schematic states 1.85 V maximum and the operating voltage is dynamically requested.
- CPU_VR_READY does not actively qualify PM_PCH_PWROK on this assembly: R1951 is unstuffed and CPUVR_PGOOD_R is pulled high by R1950.
- Do not assign a universal voltage to PLT_RESET_L: verify the board-specific I/O level and waveform.
Related Intel and Apple silicon guides
Start with S3/S0 power rails and ALL_SYS_PWRGD if the final system power-good signal is missing. Use the PM_SLP_S4_L timing guide if the sleep-state transition fails earlier. For current-generation repair examples, see the Apple silicon Mac logic-board case studies.
Conclusion
The reliable way to diagnose missing PPVCC_S0_CPU is to follow the control chain rather than replace the CPU voltage controller first: validate ALL_SYS_PWRGD and PM_SLP_S3_L, prove U1930 and CPU_VCCST_PWRGD, confirm CPU_VR_EN, verify U7200’s two source domains, then compare PWM activity with the two-phase power stage and CPU_VR_READY. Once CPU Vcore is stable, continue to PCH power-good, firmware, clock and reset diagnosis.
