A2485 820-02100 Internal Display Power-On Sequence

Summary

The 16-inch A2485 display does not switch on as one circuit. The eDP/TCON path creates the image, while a separate BCON path powers and controls the Mini-LED backlight. A MacBook can therefore have a working image with no backlight, or full backlight power with no valid eDP image.

The measured sequence starts only after the main system has become alive. U8100 MPMU enables UP710, the TCON and BCON power rails are created, the SoC establishes the eDP link, and UP800 finally produces the approximately 15V PPVOUT_LUXE supply for the backlight controller.

Board-source note: the timing, component designators, connector pins and circuit topology on this page have now been verified against the target A2485 board 820-02100 schematic and boardview, Apple drawing 051-05641. The timing values are measurements from one known-good 820-02100 and should be treated as a diagnostic reference rather than universal pass/fail limits.

The 14- and 16-inch Apple-silicon MacBook Pro families from M1 through M4 use the same broad order: system alive, panel enables, TCON and BCON rails, HPD/AUX link activity, UP800 boost enable and backlight SPI communication. Exact IC designators, net names, connector pins and millisecond timing must still be checked on the target board.

Display sequence overview

LCD_PWR_EN rising is used as the 0ms reference. Negative times occur before this edge and positive times occur after it. A bus entry in the timeline means oscilloscope activity, not a stable DC voltage.

A2485 820-02100 internal display power-on sequence showing UP710, UP701, UP730, UP800, JP600 TCON and JP900 BCON timing — A2485 internal-display power-on sequence. The blue branch powers and detects the TCON; the orange branch powers the BCON; UP800 creates the late 15V LUXE supply after its second SPMI transaction.

Circuit ownership: UP710, UP701, UP730 and UP800

Component	Confirmed function on 820-02100	Important inputs	Important outputs	Diagnostic meaning
U8100 MPMU	Owns the principal logic-board display enables.	System power state	`BL_PWR_EN`, `LCD_PWR_EN` and `BL_PMIC_PWR_EN`	If these outputs are missing, do not begin by replacing a panel-side component.
UP710 SLG4AP44015	Display power sequencer powered by `PP1V8_AON`. Pin 2 receives `LCD_PWR_EN`; pin 3 receives `PMU_SYS_ALIVE`.	`LCD_PWR_EN`, `PMU_SYS_ALIVE`	Pin 4 `EDP_PANEL_PWR_EN`; pin 11 `EDP_PANEL_1V8_EN`; pin 13 `EDP_BKLT_1V29_EN`; pin 10 `EDP_PANEL_DISCHARGE`	UP710 coordinates the TCON, BCON and SPMU enable branches.
UP701 SLG5AP1564V	Load switch for the TCON 3.8V supply.	`PP3V8_AON` and `EDP_PANEL_PWR_EN`	`PPPANEL_SW_LCD_REG`, which passes through RD892 and becomes `PP3V8_AWAKE_TCON`	If UP701 is enabled but the output is missing, check its input, output resistance and the TCON load.
UP730 TLV758P	Linear regulator for the BCON awake supply.	`PP3V8_AON` and `EDP_PANEL_PWR_EN`	`PPBCON_AWAKESW_BKLTCONN`, set to 3.2945V by RP732 49.9kΩ and RP731 10kΩ	The net is later named `PP3V8_AWAKE_BKLTCONN`, but approximately 3.29V is the designed value.
U7700 SPMU	LDO3 creates the switched BCON 1.2V rail.	`EDP_BKLT_1V29_EN` from UP710	`PP1V2_AWAKESW_BLC`	If the enable arrives but the 1.2V rail does not, inspect U7700 LDO3 and check the rail for a short.
UP800 RAA209100B	Four-switch LUXE regulator using QP800-QP803 and LP800 2.2µH to create the backlight supply.	Pin 26 `PPBUS_AON_LUXE`; pins 14/17 `PP5V_S2_MAIN`; pin 36 `PP1V2_AWAKE`; pins 34/35 SPMI data/clock; pin 21 `BL_PWR_EN_R`	`PPVOUT_LUXE` approximately 15V and active-low throttle/fault signalling	UP800 requires correct supplies, SPMI communication, enable state and a non-faulted load before it produces 15V.

A2485 820-02100 display power sequencer schematic showing UP710, UP730 and UP701 panel and backlight power enables — Display Power Sequencer schematic: UP710 converts the MPMU request into separate panel, TCON and backlight enables; UP701 switches the TCON 3.8V path and UP730 regulates the BCON supply to 3.2945V.

Complete measured timeline

Step	Time	Signal / Rail	Expected	Test Point	Meaning	If Missing
1	Prerequisite	`PP1V8_S2`	Approximately 1.8V	JP600 pin 4	Delivered to the display as the temperature/sensor 1.8V supply; it is not the principal TCON 3.8V rail.	Check the PP1V8_S2 source and JP600 path.
2	Prerequisite	`PPBUS_AON_LUXE`	Stable at the existing PPBUS_AON level	RD754 output side or UP800 pin 26	Main energy source for the LUXE regulator.	Check PPBUS_AON, RD754 and the UP800 input path.
3	Prerequisite	`PP5V_S2_MAIN`	Approximately 5V	UP800 pins 14 and 17	UP800 analogue and gate-driver support supply.	UP800 cannot operate correctly.
4	Prerequisite	`PP1V2_AWAKE`	Approximately 1.2V	UP800 pin 36	UP800 digital-interface supply.	SPMI communication with UP800 cannot be trusted.
5	-3.2s	`PMU_SYS_ALIVE`	High	UP710 pin 3	The main system has already reached the alive state.	Return to the earlier SoC/PMU startup sequence.
6	-21ms	`SPMI_DISP_BKLT_DATA` - first transaction	Valid data activity with companion SPMI clock	UP800 pins 34 and 35	The SoC first prepares or configures UP800.	`PPVOUT_LUXE` will not be enabled later.
7	-0.1ms	`BL_PWR_EN`	High	RP873 / UP800 pin 21	U8100 authorises the board-side LUXE circuit.	Check U8100 GPIO19 and the system display-on request.
8	0ms	`LCD_PWR_EN`	High	UP710 pin 2	Main timing reference; starts the display sequencer.	UP710 will not release the downstream panel enables.
9	0ms	`EDP_PANEL_PWR_EN`	High	UP710 pin 4; UP701 pin 2; UP730 pin 4	Simultaneously enables the TCON switch and BCON regulator.	Check UP710 power, inputs and output loading.
10	0.2ms	`PP3V8_AWAKE_BKLTCONN`	Approximately 3.2945V	RD966 output side or JP900 pins 49-56	UP730 has powered the BCON awake rail.	Check UP730, its feedback network, RD966 and the BCON load.
11	2.0ms	`PP3V8_AWAKE_TCON`	Approximately 3.8V	RD892 output side or JP600 pins 37/38	UP701 has powered the main TCON supply path.	Check UP701, RD892 and resistance on the TCON side.
12	2.8ms	`EDP_PANEL_1V8_EN`	High in the 1.8V domain	UP710 pin 11 or JP600 pin 32	Releases the remaining panel/TCON-side digital circuitry.	Check UP710 and the connector/display load.
13	2.8ms	`EDP_BKLT_1V29_EN`	Active/high	UP710 pin 13 and the U7700 control path	Requests the SPMU backlight LDO.	`PP1V2_AWAKESW_BLC` will remain absent.
14	3.0ms	`PP1V2_AWAKESW_BLC`	Approximately 1.2V	U7700 LDO3 output or JP900 pins 43-46	Supplies the BCON digital/PMIC logic.	Check the enable, U7700 LDO3 and rail resistance.
15	3.1ms	`BKLT_BOOST_THROTTLE_CONN_L`	High, pulled up to the BCON 1.2V rail	JP900 pin 10	Active-low backlight fault/shutdown line. High means no shutdown request.	A low level can inhibit or kill the backlight boost.
16	5.6ms	`BL_PMIC_PWR_EN`	High	JP900 pin 5	U8100 enables the BCON PMIC. This signal is present even with the display disconnected.	Check U8100 GPIO22 and the board-side path.
17	Before AUX	`LPDP_INT_HPD`	Asserted	JP600 pin 34; no dedicated board test point	The TCON reports that the internal display is present.	Suspect TCON power, connector, cable or display assembly.
18	125ms	`LPDP_INT_AUX`	Bidirectional differential activity	JP600 pins 27/29	SoC and TCON exchange capabilities, status and link-training information.	The panel may be powered but cannot establish the eDP link.
19	180ms	`SPI_TCON_CLK_CONN`	Clock activity	JP600 pin 28	Later SoC-to-TCON SPI communication.	On the tested board, its absence did not prevent basic image and backlight, so it is not the first power checkpoint.
20	219.8ms	`SPMI_DISP_BKLT_DATA` - second transaction	Second valid SPMI burst	UP800 pins 34/35	The SoC now commands UP800 to create the LUXE output.	All early rails can be present while the 15V output remains missing.
21	220ms	`PPVOUT_LUXE`	Approximately 15V	JP900 pins 21-38	Main power supply delivered to the BCON.	Check SPMI, throttle state, UP800, VGD, QP800-QP803, LP800 and the output load.
22	223ms	`SPI_DISP_BKLT_MOSI_CONN`	Data activity with a valid SPI clock	MOSI JP900 pin 6; clock JP900 pin 2	The SoC configures the BCON after its power rails are present.	Missing SPI clock is consistent with a dim Apple logo followed by a restart.
23	460ms	`I2C_SMC_SNS0_SDA_1V8`	Later I²C activity	JP600 pin 8 with SCL on pin 6	Late display sensor and monitoring communication.	Do not treat it as an early panel-power prerequisite.
24	No activity observed	`UART_TCON_D2R_1V8`	No waveform required in this capture	JP600 pin 14	Optional or diagnostic TCON communication path.	Its inactivity alone is not a fault.
25	No activity observed	`I2C_TCON_BKLT_SDA_1V8`	No waveform required in this capture	JP900 pin 3 with SCL on pin 1	Optional or unused during the captured startup.	Its inactivity alone is not a fault.
26	No test point	`DISP_BKLT_LSYNC`	Line-level synchronisation	JP900 pin 4	Coordinates backlight operation with display lines.	Infer from the final result unless connector-level probing is available.
27	No test point	`DISP_2DBL_FSYNC`	Frame-level synchronisation	JP900 pin 14	Coordinates the backlight with the display frame.	Not a practical first-line logic-board measurement.

JP600 eDP and TCON path

UP710 receives LCD_PWR_EN and PMU_SYS_ALIVE. Its EDP_PANEL_PWR_EN output enables UP701. UP701 passes PP3V8_AON into the TCON branch, where RD892 and its current-sense amplifier monitor the load before the rail reaches JP600 as PP3V8_AWAKE_TCON.

After the 3.8V rail and EDP_PANEL_1V8_EN are present, the TCON asserts LPDP_INT_HPD. The SoC then uses the AUX pair for display discovery, status exchange and eDP link setup. HPD and AUX are therefore much stronger evidence of a functioning TCON than a single rail measurement.

PP1V8_S2 is present at JP600 pin 4, but the uploaded schematic identifies this connection as the display-temperature/sensor supply. It should not be described as the TCON's only or principal operating rail.

A2485 820-02100 JP600 eDP TCON display connector schematic with LPDP lanes, AUX, HPD, TCON SPI and display power rails — JP600 eDP/TCON connector reference: LPDP data and AUX pairs, TCON SPI, HPD, sensor I²C, `EDP_PANEL_1V8_EN` and `PP3V8_AWAKE_TCON`.

JP900 BCON and backlight path

The uploaded schematic identifies the backlight connector as JP900, not P900. UP730 provides the approximately 3.29V awake supply, while U7700 LDO3 creates PP1V2_AWAKESW_BLC. U8100 separately sends BL_PMIC_PWR_EN to JP900.

UP800 does not create 15V as soon as its input power appears. The first SPMI transaction occurs before LCD_PWR_EN and prepares the controller. The second transaction occurs around 219.8ms and is immediately followed by PPVOUT_LUXE at approximately 220ms.

UP800 is a four-switch regulator. Its gate-driver voltage VGD drives QP800-QP803 around LP800. If the supplies, SPMI and enables are correct but PPVOUT_LUXE is absent, check VGD, the MOSFET gate waveforms, both switch nodes, LP800, the output capacitors and the disconnected-panel result.

A2485 820-02100 UP800 RAA209100B LUXE backlight driver schematic with QP800 to QP803, LP800 and PPVOUT_LUXE — UP800 LUXE backlight-driver reference: PPBUS_AON input, SPMI and enable control, VGD gate drive, four switching MOSFETs, LP800 and the approximately 15V PPVOUT_LUXE output.

A2485 820-02100 JP900 BCON connector schematic with PPVOUT_LUXE, BCON 3.8V and 1.2V rails, SPI, throttle and sync signals — JP900 BCON connector reference: PPVOUT_LUXE, the 3.29V and 1.2V BCON rails, BL_PMIC_PWR_EN, SPI communication, active-low throttle feedback and line/frame synchronisation.

Current sensing and protection

RD754 - LUXE PPBUS input

RD754 is a 0.003Ω four-terminal shunt between PPBUS_AON and PPBUS_AON_LUXE. UD770 is an INA190A3 current-sense amplifier with 100x gain. The schematic design note gives 4.687A EDP, approximately 14.061mV across the shunt and a 5A range.

The current is calculated from I = ΔV / 0.003Ω. Because the resistance is only 3mΩ, the resistor will normally look like a direct connection in continuity mode.

RD966 - BCON 3.29V load

RD966 is a 0.035Ω four-terminal shunt between PPBCON_AWAKESW_BKLTCONN and PP3V8_AWAKE_BKLTCONN. UD960 is an INA190A4 current-sense amplifier with 200x gain. The design note gives 0.2A EDP, approximately 7mV across the shunt and a 0.3A range.

The sense terminals are separate Kelvin connections even though both power ends appear connected on a multimeter.

A2485 820-02100 RD754 PPBUS_AON_LUXE current-sense schematic with UD770 INA190A3 amplifier — RD754 LUXE input-current sensing: 0.003Ω shunt, UD770 100x amplifier and BKLT_HS_ISENSE output.

A2485 820-02100 RD966 display backlight 3.8V current-sense schematic with UD960 INA190A4 amplifier — RD966 BCON awake-current sensing: 0.035Ω shunt, UD960 200x amplifier and BKLTCONN_3V8_ISENSE output.

Practical diagnostic order

Confirm PMU_SYS_ALIVE. If it is missing, the fault is earlier than the display sequence.
Confirm UP800's prerequisite rails: PPBUS_AON_LUXE, PP5V_S2_MAIN and PP1V2_AWAKE.
Check LCD_PWR_EN and UP710 outputs. Find the earliest missing output rather than starting at the 15V rail.
For no image, follow EDP_PANEL_PWR_EN to UP701, then check PP3V8_AWAKE_TCON, EDP_PANEL_1V8_EN, HPD and AUX.
For image with no backlight, follow the UP730/U7700 branch, confirm the 3.29V and 1.2V BCON rails, and verify that BKLT_BOOST_THROTTLE_CONN_L remains high.
Confirm both SPMI transactions at UP800. Data activity without the companion clock does not prove a valid transaction.
If the second SPMI transaction is present but 15V is missing, check UP800 VGD, QP800-QP803, LP800, RD754 and the output load.
If 15V is present but the Apple logo is dim and the Mac restarts, check the BCON SPI clock before interpreting MOSI activity.

Important: UART_TCON_D2R_1V8 and I2C_TCON_BKLT_SDA_1V8 showed no activity in the known-good capture. Their inactivity alone should not be diagnosed as the cause of a no-image or no-backlight fault. DISP_BKLT_LSYNC and DISP_2DBL_FSYNC have no convenient logic-board test points.

Terminology

Term	Meaning	Repair significance
TCON	Timing controller inside the display assembly	Receives eDP data and produces the timing needed to drive the LCD panel.
BCON	Backlight controller inside the display assembly	Controls the Mini-LED backlight independently of the TCON image path.
SPMI	System Power Management Interface	Two-wire clock/data bus used by the SoC to configure power-management devices such as UP800.
HPD	Hot Plug Detect	Panel-present indication from the internal display to the SoC.
AUX	DisplayPort auxiliary channel	Bidirectional link used for display discovery, status and link training.
VGD	Gate-driver voltage	Supply used by UP800 to drive the external switching MOSFET gates.
ISENSE	Current sensing	A small voltage across a low-ohm shunt is amplified so the PMU can monitor load current.
Signal ending in _L	Active-low logic	Low means asserted. `BKLT_BOOST_THROTTLE_CONN_L` being low reports or requests a shutdown condition.

Diagnostic conclusion: the most useful measurement is the earliest missing or withdrawn event. An absent PPVOUT_LUXE does not by itself prove that UP800 is defective, because the controller intentionally withholds the 15V output when an earlier power, enable, SPMI or fault-feedback condition is incorrect.